Data Sheet ADF4360-0
Rev. D | Page 21 of 24
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The leads on the chip scale package (CP-24) are rectangular. The
printed circuit board pad for these should be 0.1 mm longer
than the package lead length and 0.05 mm wider than the
package lead width. The lead should be centered on the pad to
ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that
shorting is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at a 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 ounce of
copper to plug the via.
The user should connect the printed circuit thermal pad to
AGND. This is internally connected to AGND.
OUTPUT MATCHING
There are a number of ways to match the output of the ADF4360-0
for optimum operation; the most basic is to use a 50 Ω resistor
to V
VCO
. A dc bypass capacitor of 100 pF is connected in series,
as shown in Figure 20. Because the resistor is not frequency
dependent, this provides a good broadband match. The output
power in this circuit typically gives −6.5 dBm output power into
a 50 Ω load.
100pF
04644-024
RF
OUT
V
VCO
50
51
Figure 20. Simple ADF4360-0 Output Stage
A better solution is to use a shunt inductor (acting as an RF
choke) to V
VCO
. This gives a better match than a resistor and,
therefore, more output power. Additionally, a series inductor is
added after the dc bypass capacitor to provide a resonant LC
circuit. This tunes the oscillator output and provides approximately
10 dB additional rejection of the second harmonic. The shunt
inductor needs to be a relatively low value (<10 nH).
Experiments have shown that the circuit shown in Figure 21
provides an excellent match to 50 Ω over the operating range of
the ADF4360-0. This gives approximately −4 dBm output power
across the frequency range of the ADF4360-0. Both single-ended
architectures can be examined using the EV-ADF4360-0EB1Z
evaluation board.
3.9nH
47nH
1.5pF
04644-025
RF
OUT
V
VCO
50
Figure 21. Differential ADF4360-0 Output Stage
If the user does not need the differential outputs available on
the ADF4360-0, the user may either terminate the unused
output or combine both outputs using a balun. The circuit in
Figure 22 shows how best to combine the outputs.
1nH
3.6nH
47nH
3.6nH
1.5pF
10pF
1.5pF
50
1nH
RF
OUT
A
V
VCO
RF
OUT
B
04644-026
Figure 22. Balun for Combining ADF4360-0 RF Outputs
The circuit in Figure 22 is a lumped-lattice-type LC balun. It is
designed for a center frequency of 2.6 GHz and outputs −1 dBm
at this frequency. The series 1 nH inductor is used to tune out
any parasitic capacitance due to the board layout from each
input, and the remainder of the circuit is used to shift the
output of one RF input by +90° and the second by −90°, thus
combining the two. The action of the 3.6 nH inductor and the
1.5 pF capacitor accomplishes this. The 12 nH is used to provide
an RF choke to feed the supply voltage, and the 10 pF capacitor
provides the necessary dc block. To ensure good RF performance,
the circuits in Figure 20 and Figure 22 are implemented with
Coilcraft 0402/0603 inductors and AVX 0402 thin-film capacitors.
Alternatively, instead of the LC balun shown in Figure 22, both
outputs can be combined using a 180° rat-race coupler.
