OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADF4360-0BCPZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet ADF4360-0
Rev. D | Page 3 of 24
SPECIFICATIONS
1
AV
DD
= DV
DD
= V
VCO
= 3.3 V ± 10%; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter B Version Unit Test Conditions/Comments
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency
MHz min/max
For f < 10 MHz, use dc-coupled
CMOS-compatible square wave, slew rate > 21 V/µs.
REF
IN
Input Sensitivity 0.7/AV
DD
V p-p min/max AC-coupled.
0 to AV
DD
V max CMOS-compatible.
REF
IN
Input Capacitance 5.0 pF max
REF
IN
Input Current
µA max
PHASE DETECTOR
Phase Detector Frequency
2
8 MHz max
CHARGE PUMP
I
CP
Sink/Source
3
With R
SET
= 4.7 kΩ.
High Value 2.5 mA typ
Low Value
mA typ
R
SET
Range 2.7/10 kΩ
I
CP
Three-State Leakage Current 0.2 nA typ
Sink and Source Current Matching 2 % typ 1.25 V ≤ V
CP
≤ 2.5 V.
I
CP
vs. V
CP
1.5 % typ 1.25 V ≤ V
CP
≤ 2.5 V.
I
CP
vs. Temperature 2 % typ V
CP
= 2.0 V.
LOGIC INPUTS
V
INH
, Input High Voltage 1.5 V min
V
INL
, Input Low Voltage
V max
I
INH
/I
INL
, Input Current ±1 µA max
C
IN
, Input Capacitance 3.0 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage DV
DD
– 0.4 V min CMOS output chosen.
I
OH
, Output High Current 500 µA max
V
OL
, Output Low Voltage 0.4 V max I
OL
= 500 µA.
POWER SUPPLIES
AV
DD
3.0/3.6 V min/V max
DV
DD
AV
DD
V
VCO
AV
DD
AI
DD
4
10 mA typ
DI
DD
4
2.5 mA typ
I
VCO
4, 5
19.0 mA typ I
CORE
= 10 mA.
I
RFOUT
4
3.5 to 11.0 mA typ RF output stage is programmable.
Low Power Sleep Mode
4
7 µA typ
RF OUTPUT CHARACTERISTICS
5
VCO Output Frequency 2400/2725 MHz min/max I
CORE
= 15 mA.
VCO Sensitivity 56 MHz/V typ
Lock Time
6
250 µs typ To within 10 Hz of final frequency.
Frequency Pushing (Open-Loop)
MHz/V typ
Frequency Pulling (Open-Loop) 15 kHz typ Into 2.00 VSWR load.
Harmonic Content (Second) −30 dBc typ
Harmonic Content (Third) −39 dBc typ
Output Power
5, 7
−13/−6.5 dBm typ Programmable in 3 dB steps. See Table 7.
Output Power Variation ±3 dB typ For tuned loads, see the Output Matching section.
VCO Tuning Range 1.25/2.50 V min/max
VCO Tuning Port Leakage Current 0.2 nA typ
ADF4360-0 Data Sheet
Rev. D | Page 4 of 24
Parameter B Version Unit Test Conditions/Comments
NOISE CHARACTERISTICS
5
VCO Phase-Noise Performance
8
−111 dBc/Hz typ At 100 kHz offset from carrier.
−133 dBc/Hz typ At 1 MHz offset from carrier.
−140 dBc/Hz typ At 3 MHz offset from carrier.
dBc/Hz typ
At 10 MHz offset from carrier.
Synthesizer Phase-Noise Floor
9
−172 dBc/Hz typ At 25 kHz PFD frequency.
−163 dBc/Hz typ At 200 kHz PFD frequency.
−147 dBc/Hz typ At 8 MHz PFD frequency.
Phase Noise Figure of Merit
9
−216 dBc/Hz typ
In-Band Phase Noise
10, 11
−80 dBc/Hz typ At 1 kHz offset from carrier.
RMS Integrated Phase Error
12
Degrees typ
100 Hz to 100 kHz.
Spurious Signals due to PFD Frequency
11, 13
−75 dBc typ
Level of Unlocked Signal with MTLD Enabled −45 dBm typ
1
Operating temperature range is: –40°C to +85°C.
2
Guaranteed by design. Sample tested to ensure compliance.
3
I
CP
is internally modified to maintain constant loop gain over the frequency range.
4
T
A
= 25°C; AV
DD
= DV
DD
= V
VCO
= 3.3 V; P = 32.
5
These characteristics are guaranteed for VCO core power = 10 mA.
6
Jumping from 2.4 GHz to 2.725 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7
Using 50 Ω resistors to V
VCO
into a 50 Ω load. For tuned loads, see the Output Matching section.
8
The noise of the VCO is measured in open-loop conditions.
9
The synthesizer phase-noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). The
phase noise figure of merit subtracts 10 log (PFD frequency).
10
The phase noise is measured with the EV-ADF4360-0EB1Z Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REF
IN
for the
synthesizer; offset frequency = 1 kHz.
11
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; N = 13000; Loop B/W = 10 kHz.
12
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; N=2600; Loop B/W = 25 kHz.
13
The spurious signals are measured with the EV-ADF4360-0EB1Z Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REF
IN
for
the synthesizer; f
REFOUT
= 10 MHz at 0 dBm.
Data Sheet ADF4360-0
Rev. D | Page 5 of 24
TIMING CHARACTERISTICS
1
AV
DD
= DV
DD
= V
VCO
= 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Limit at T
MIN
to T
MAX
(B Version) Unit Test Conditions/Comments
t
1
20 ns min LE Setup Time
t
2
10 ns min DATA to CLOCK Setup Time
t
3
10 ns min DATA to CLOCK Hold Time
t
4
25 ns min CLOCK High Duration
t
5
25 ns min CLOCK Low Duration
t
6
10 ns min CLOCK to LE Setup Time
t
7
20 ns min LE Pulse Width
1
See the Power-Up section for the recommended power-up procedure for this device.
CLOC
K
DATA
LE
LE
DB23 (MSB) DB22 DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
04644-002
Figure 2. Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

ADF4360-0BCPZRL

Mfr. #:
Buy ADF4360-0BCPZRL
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Intg Integer-N VCO Out Freq 2400-2725
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet