ADF4360-0BCPZRL Datasheet ADF4360-0BCPZ, ADF4360-0BCPZRL7, ADF4360-0BCPZRL | P19-P21

ADF4360-0 Data Sheet

Rev. D | Page 18 of 24

CONTROL LATCH

With (C2, C1) = (0, 0), the control latch is programmed. Table 7

shows the input data format for programming the control latch.

Prescaler Value

In the ADF4360-0, P2 and P1 in the control latch set the

prescaler values.

Power-Down

DB21 (PD2) and DB20 (PD1) provide programmable power-

down modes.

In the programmed asynchronous power-down, the device

powers down immediately after latching a 1 into Bit PD1,

with the condition that PD2 has been loaded with a 0. In the

programmed synchronous power-down, the device power-

down is gated by the charge pump to prevent unwanted frequency

jumps. Once the power-down is enabled by writing a 1 into Bit

PD1 (on the condition that a 1 has also been loaded to PD2),

the device goes into power-down on the second rising edge of

the R counter output, after LE goes high. When the CE pin is

low, the device is immediately disabled regardless of the state of

PD1 or PD2.

When a power-down is activated (either synchronous or

asynchronous mode), the following events occur:

• All active dc current paths are removed.

• The R, N, and timeout counters are forced to their load

state conditions.

• The charge pump is forced into three-state mode.

• The digital lock detect circuitry is reset.

• The RF outputs are debiased to a high impedance state.

• The reference input buffer circuitry is disabled.

• The input register remains active and capable of loading

and latching data.

Charge Pump Currents

CPI3, CPI2, and CPI1 in the ADF4360-0 determine

Current Setting 1.

CPI6, CPI5, and CPI4 determine Current Setting 2. See the

truth table in Table 7.

Output Power Level

Bits PL1 and PL2 set the output power level of the VCO. See the

truth table in Table 7.

Mute-Till-Lock Detect

DB11 of the control latch in the ADF4360-0 is the mute-till-lock

detect bit. This function, when enabled, ensures that the RF outputs

are not switched on until the PLL is locked.

CP Gain

DB10 of the control latch in the ADF4360-0 is the charge pump

gain bit. When it is programmed to a 1, Current Setting 2 is

used. When it is programmed to a 0, Current Setting 1 is used.

Charge Pump Three-State

This bit puts the charge pump into three-state mode when

programmed to a 1. It should be set to 0 for normal operation.

Phase Detector Polarity

The PDP bit in the ADF4360-0 sets the phase detector polarity.

The positive setting enabled by programming a 1 is used when

using the on-chip VCO with a passive loop filter or with an

active non-inverting filter. It can also be set to 0. This is

required, if an active inverting loop filter is used.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1. See

the truth table in Table 7.

Counter Reset

DB4 is the counter reset bit for the ADF4360-0. When this is 1,

the R counter and the A, B counters are reset. For normal

operation, this bit should be 0.

Core Power Level

PC1 and PC2 set the power level in the VCO core. The

recommended setting is 10 mA. See the truth table in Table 7.

Data Sheet ADF4360-0

Rev. D | Page 19 of 24

N COUNTER LATCH

With (C2, C1) = (1, 0), the N counter latch is programmed.

Table 8 shows the input data format for programming the

N counter latch.

A Counter Latch

A5 to A1 program the 5-bit A counter. The divide range is 0

(00000) to 31 (11111).

Reserved Bits

DB7 is a spare bit that is reserved. It should be programmed to 0.

B Counter Latch

B13 to B1 program the B counter. The divide range is 3

(00.....0011) to 8191 (11....111).

Overall Divide Range

The overall divide range is defined by ((P × B) + A), where P is

the prescaler value.

CP Gain

DB21 of the N counter latch in the ADF4360-0 is the charge

pump gain bit. When this is programmed to 1, Current Setting 2

is used. When programmed to 0, Current Setting 1 is used. This bit

can also be programmed through DB10 of the control latch. The bit

always reflects the latest value written to it, whether this is through

the control latch or the N counter latch.

Divide-by-2

DB22 is the divide-by-2 bit. When set to 1, the output divide-by-2

function is chosen. When it is set to 0, normal operation occurs.

Divide-by-2 Select

DB23 is the divide-by-2 select bit. When programmed to 1, the

divide-by-2 output is selected as the prescaler input. When set

to 0, the fundamental is used as the prescaler input. For

example, using the output divide-by-2 feature and a PFD

frequency of 200 kHz, the user needs a value of N = 13,000 to

generate 1,500 MHz. With the divide-by-2 select bit high, the

user may keep N = 6,500.

R COUNTER LATCH

With (C2, C1) = (0, 1), the R counter latch is programmed.

Table 9 shows the input data format for programming the

R counter latch.

R Counter

R1 to R14 set the counter divide ratio. The divide range is 1

(00......001) to 16383 (111......111).

Antibacklash Pulse Width

DB16 and DB17 set the antibacklash pulse width.

Lock Detect Precision

DB18 is the lock detect precision bit. This bit sets the number of

reference cycles with less than 15 ns phase error for entering the

locked state. With LDP at 1, five cycles are taken; with LDP at 0,

three cycles are taken.

Test Mode Bit

DB19 is the test mode bit (TMB) and should be set to 0. With

TMB = 0, the contents of the test mode latch are ignored and

normal operation occurs as determined by the contents of the

control latch, R counter latch, and N counter latch. Note that

test modes are for factory testing only and should not be

programmed by the user.

Band Select Clock

These bits set a divider for the band select logic clock input. The

output of the R counter is by default the value used to clock the

band select logic, but, if this value is too high (>1 MHz), a

divider can be switched on to divide the R counter output to a

smaller value (see Table 9).

Reserved Bits

DB23 to DB22 are spare bits that are reserved. They should be

programmed to 0.

ADF4360-0 Data Sheet

Rev. D | Page 20 of 24

APPLICATIONS INFORMATION

FIXED FREQUENCY LO

Figure 17 shows the ADF4360-0 used as a fixed frequency LO at

2.6 GHz. The low-pass filter was designed using ADIsimPLL for a

channel spacing of 8 MHz and an open-loop bandwidth of 40 kHz.

The maximum PFD frequency of the ADF4360-0 is 8 MHz.

Because using a larger PFD frequency allows users to use a smaller

N, the in-band phase noise is reduced to as low as possible,

–100 dBc/Hz. The 40 kHz bandwidth is chosen to be just greater

than the point at which the open-loop phase noise of the VCO is

–100 dBc/Hz, thus giving the best possible integrated noise. The

typical rms phase noise (100 Hz to 100 kHz) of the LO in this

configuration is 0.35°. The reference frequency is from a 16 MHz

TCXO from Fox; thus, an R value of 2 is programmed. Taking into

account the high PFD frequency and its effect on the band select

logic, the band select clock divider is enabled. In this case, a value of

8 is chosen. A very simple pull-up resistor and dc blocking

capacitor complete the RF output stage.

SPI COMPATIBLE SERIAL BUS

ADF4360-0

VCO

FOX

801BE-160

16MHz

VCO

CPGND AGND DGND

OUT

1nF

560pF 270pF

8.2nF

51

100pF

1nF1nF

10F

4.7k

1.5k

3k

SET

DATA

CLK

REF

TUNE

CE MUXOUT

2023221

VDD

LOCK

DETECT

04644-021

3 8 9 10 11 22 15

Figure 17. Fixed Frequency LO

INTERFACING

The ADF4360-0 has a simple SPI®-compatible serial interface

for writing to the device. CLK, DATA, and LE control the data

transfer. When LE goes high, the 24 bits that have been clocked

into the appropriate register on each rising edge of CLK are

transferred to the appropriate latch. See Figure 2 for the timing

diagram and Table 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible is 833 kHz or

one update every 1.2 μs. This is more than adequate for systems

that have typical lock times in hundreds of microseconds.

ADuC812 Interface

Figure 18 shows the interface between the ADF4360-0 and the

ADuC812 MicroConverter®. Because the ADuC812 is based on

an 8051 core, this interface can be used with any 8051 based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the the ADF4360-0

needs a 24-bit word, which is accomplished by writing three

8-bit bytes from the MicroConverter to the device. When the

third byte has been written, the LE input should be brought

high to complete the transfer.

04644-022

ADuC812

ADF4360-0

SCLK

SDATA

MUXOUT

(LOCK DETECT)

SCLOCK

MOSI

I/O PORTS

Figure 18. ADuC812 to ADF4360-0 Interface

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and detect lock (MUXOUT configured as lock

detect and polled by the port input). When operating in the

described mode, the maximum SCLOCK rate of the ADuC812

is 4 MHz. This means that the maximum rate at which the

output frequency can be changed is 166 kHz.

ADSP-2181 Interface

Figure 19 shows the interface between the ADF4360-0 and the

ADSP-2181 digital signal processor. The ADF4360-0 needs a

24-bit serial word for each latch write. The easiest way to

accomplish this using the ADSP-2181 is to use the autobuffered

transmit mode of operation with alternate framing. This provides

a means for transmitting an entire block of serial data before an

interrupt is generated.

04644-023

ADSP-2181

ADF4360-0

SCLK

SDATA

MUXOUT

(LOCK DETECT)

SCLOCK

MOSI

TFS

I/O PORTS

Figure 19. ADSP-2181 to ADF4360-0 Interface

Set up the word length for 8 bits and use three memory

locations for each 24-bit word. To program each 24-bit latch,

store the 8-bit bytes, enable the autobuffered mode, and write to

the transmit register of the DSP. This last operation initiates the

autobuffer transfer.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

ADF4360-0BCPZRL

Mfr. #:

Buy ADF4360-0BCPZRL

Manufacturer:

Analog Devices Inc.

Description:

Phase Locked Loops - PLL Intg Integer-N VCO Out Freq 2400-2725

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ADF4360-0BCPZRL

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