MAX11600–MAX11605
SCL is high (Figure 5). A repeated START condition (Sr)
can be used in place of a STOP condition to leave the
bus active and in its current timing mode (see the
HS
Mode
section).
Acknowledge Bits
Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (A). Both
the master and the MAX11600–MAX11605 (slave) gener-
ate acknowledge bits. To generate an acknowledge bit,
the receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the clock
pulse (Figure 6). To generate a not acknowledge bit, the
receiver allows SDA to be pulled high before the rising
edge of the acknowledge-related clock pulse and leaves
it high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master should reattempt
communication at a later time.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by a
slave address. When idle, the MAX11600–MAX11605
continuously wait for a START condition followed by
their slave address. When the MAX11600–MAX11605
recognize their slave address, they are ready to accept
or send data. The slave address has been factory pro-
grammed and is always 1100100 for the MAX11600/
MAX11601, 1101101 for MAX11602/MAX11603, and
1100101 for MAX11604/MAX11605 (Figure 7). The least
significant bit (LSB) of the address byte (R/W) deter-
mines whether the master is writing to or reading from
the MAX11600–MAX11605 (R/W = zero selects a write
condition. R/W = 1 selects a read condition). After
receiving the address, the MAX11600–MAX11605
(slave) issue an acknowledge by pulling SDA low for
one clock cycle.
Bus Timing
At power-up, the MAX11600–MAX11605 bus timing
defaults to fast mode (F/S mode), allowing conversion
rates up to 44ksps. The MAX11600–MAX11605 must
operate in high-speed mode (HS mode) to achieve
conversion rates up to 188ksps. Figure 1 shows the bus
timing for the MAX11600–MAX11605 2-wire interface.
HS Mode
At power-up, the MAX11600–MAX11605 bus timing is
set for F/S mode. The master selects HS mode by
addressing all devices on the bus with the HS mode
master code 0000 1XXX (X = don’t care). After success-
fully receiving the HS-mode master code, the
MAX11600–MAX11605 issues a not acknowledge,
allowing SDA to be pulled high for one clock cycle
(Figure 8). After the not acknowledge, the
MAX11600–MAX11605 are in HS mode. The master must
then send a repeated START followed by a slave
address to initiate HS mode communication. If the mas-
ter generates a STOP condition, the MAX11600–
MAX11605 return to F/S mode.
Configuration/Setup Bytes (Write Cycle)
Write cycles begin with the master issuing a START
condition followed by 7 address bits (Figure 7) and 1
write bit (R/W = zero). If the address byte is successful-
ly received, the MAX11600–MAX11605 (slave) issue an
acknowledge. The master then writes to the slave. The
slave recognizes the received byte as the setup byte
(Table 1) if the most significant bit (MSB) is 1. If the
MSB is zero, the slave recognizes that byte as the con-
figuration byte (Table 2). The master can write either 1
or 2 bytes to the slave in any order (setup byte then
configuration byte; configuration byte then setup byte;
setup byte only; configuration byte only; Figure 9). If the
slave receives bytes successfully, it issues an acknowl-
edge. The master ends the write cycle by issuing a
STOP condition or a repeated START condition. When
operating in HS mode, a STOP condition returns the
bus to F/S mode (see the
HS Mode
section).
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
12 ______________________________________________________________________________________
