B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE: t
ACQ
+ t
CONV
7.6
µ
s PER CHANNEL.
S
1
SLAVE ADDRESS A
711
R
CLOCK STRETCH
NUMBER OF BITS
P or Sr
1
8
RESULT
A
1
A. SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
711
R
CLOCK STRETCH
A
NUMBER OF BITS
P OR Sr
1
8
RESULT 1
A
1
A
8
RESULT 2
A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
t
CONV1
CLOCK STRETCH
t
ACQ1
t
CONV2
t
ACQ2
t
CONVN
t
ACQN
t
CONV
t
ACQ
1
1
Figure 10. Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
t
CONV1
t
ACQ1
t
CONV2
t
ACQ2
t
CONVN
t
ACQN
t
CONV
t
ACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
711
R
S
1
A
711
R P OR Sr
1
8
A
1
A
8
A
8
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11. External Clock Mode Read Cycles
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1
For the MAX11600/MAX11601, CS3 and CS2 are internally set to zero. For the MAX11602/MAX11603, CS3 is internally set to zero.
2
When SEL1 = 1, a single-ended read of AIN3/REF (MAX11600/MAX11601) or AIN11/REF (MAX11604/MAX11605) returns GND. This
does not apply to the MAX11602/MAX11603 as each provides separate pins for AIN7 and REF.
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS3
1
CS2
1
CS1 CS0 AIN0 AIN1 AIN2 AIN3
2
AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11
2
GN D
0000+ -
0001 + -
0010 + -
0011 + -
0100 + -
0101 + -
0110 + -
0111 + -
1000 + -
1001 +-
1010 +-
1011 +-
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS3
2
CS2
2
CS1 CS0 AIN0 AIN1 AIN2 AIN3
2
AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11
3
0000+-
0001-+
0010 +-
0011 -+
0100 +-
0101 -+
0110 +-
0111 -+
1000 +-
1001 -+
1010 +-
1011 -+
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4. Channel Selection in Pseudo-Differential Mode (SGL/DIF = 0)
1
1
When scanning multiple channels (SCAN0 = 0), CS0 = 0 causes the even-numbered channel-select bits to be scanned, while CS0 = 1
causes the odd-numbered channel-select bits to be scanned. For example, if the MAX11604/MAX11605 SCAN[1:0] = 00 and CS[3:0] =
1010, a pseudo-differential read returns AIN0–AIN1, AIN2–AIN3, AIN4–AIN5, AIN6–AIN7, AIN8–AIN9, and AIN10–AIN11. If the
MAX11604/MAX11605 SCAN[1:0] = 00 and CS[3:0] = 1011, a pseudo-differential read returns AIN1–AIN0, AIN3–AIN2, AIN5–AIN4,
AIN7–AIN6, AIN9–AIN8, and AIN11–AIN10.
2
For the MAX11600/MAX11601, CS3 and CS2 are internally set to zero. For the MAX11602/MAX11603, CS3 is internally set to zero.
3
When SEL1 = 1, a pseudo-differential read between AIN2 and AIN3/REF (MAX11600/MAX11601) or AIN10 and AIN11/REF
(MAX11604/MAX11605) returns the difference between GND and AIN2 or AIN10, respectively. For example, a pseudo-differential
read of 1011 returns the negative difference between AIN10 and GND. This does not apply to the MAX11602/MAX11603 as each pro-
vides separate pins for AIN7 and REF.

MAX11603EEE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 8-Bit 8Ch 188ksps 3.6V Precision ADC
Lifecycle:
New from this manufacturer.
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