MAX11600–MAX11605
External Reference
The external reference can range from 1.0V to V
DD
. For
maximum conversion accuracy, the reference must be
able to deliver up to 30µA and have an output impedance
of 1k or less. If the reference has a higher output imped-
ance or is noisy, bypass it to GND as close as possible to
AIN_/REF (MAX11600/MAX11601/MAX11604/MAX11605)
or REF (MAX11602/MAX11603) with a 0.1µF capacitor.
Transfer Functions
Output data coding for the MAX11600–MAX11605 is
binary in unipolar mode and two’s complement binary in
bipolar mode with 1 LSB = V
REF
/2
N
where N is the num-
ber of bits (8). Code transitions occur halfway between
successive-integer LSB values. Figures 12 and 13 show
the input/output (I/O) transfer functions for unipolar and
bipolar operations, respectively.
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3–CS0 (default setting).
0 1 Converts the input selected by CS3–CS0 eight times.*
MAX11600/MAX11601: Scans upper half of channels.
Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0, AIN1, and
AIN2, the scanning stops at AIN2 (MAX11600/MAX11601).
MAX11602/MAX11603: Scans upper quartile of channels.
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the scanning
stops at AIN6 (MAX11602/MAX11603).
10
MAX11604/MAX11605: Scans upper half of channels.
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the scanning
stops at AIN6 (MAX11604/MAX11605).
1 1 Converts the channel selected by CS3–CS0.*
Table 5. Scanning Configuration
*
When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11 and converting continues
until a not acknowledge occurs.
SEL2 SEL1 SEL0
REFERENCE
VOLTAGE
AIN_/REF
(MAX11600/
MAX11601/
MAX11604/
MAX11605)
REF
(MAX11602/
MAX11603)
INTERNAL
REFERENCE STATE
00X V
DD
Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6. Reference Voltage, AIN_/REF, and REF Format
X = Don’t care.
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap config-
urations are not recommended since the layout should
ensure proper separation of analog and digital traces. Do
not run analog and digital lines parallel to each other, and
do not lay out digital signal paths underneath the ADC
package. Use separate analog and digital PCB ground
sections with only one star point (Figure 14) connecting
the two ground systems (analog and digital). For lowest
noise operation, ensure the ground return to the star
ground’s power supply is low impedance and as short as
possible. Route digital signals far away from sensitive
analog and reference inputs.
High-frequency noise in the power supply (V
DD
) could
influence the proper operation of the ADC’s fast
comparator. Bypass V
DD
to the star ground with a
0.1µF capacitor located as close as possible to the
MAX11600–MAX11605 power-supply pin. Minimize
capacitor lead length for best supply-noise rejection,
and add an attenuation resistor (5) if the power sup-
ply is extremely noisy.
INPUT VOLTAGE (LSB)
OUTPUT CODE
1...111
1...110
1...101
1...100
0...000
0...001
0...010
0...011
23
256
V
REF
1 LSB =
1 253 255254
REF
2560 252
Figure 12. Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE
(TWO'S COMPLEMENT)
0...111
0...110
0...101
0...100
1...000
1...001
1...010
1...011
-1-126 -125
256
V
REF
1 LSB =
0+1-127 +125 +127+126
0...000
0...001
1...111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13. Bipolar Transfer Function
3V/5V
V
LOGIC
= 3V/5V
GND
SUPPLIES
DGND3V/5V
GND
0.1µF
V
DD
DIGITAL
CIRCUITRY
MAX11600–
MAX11605
R* = 5
*OPTIONAL
Figure 14. Power-Supply and Grounding Connections
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The INL
is measured using the end point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (t
AJ
) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (t
AD
) is the time between the rising
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
SNR = (6.02
N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is computed by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SINAD (dB) = 20
log (Signal
RMS
/Noise
RMS
)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun-
damental itself. This is expressed as:
where V
1
is the fundamental amplitude, and V
2
through
V
5
are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
Chip Information
PROCESS: BiCMOS
THD VVVV V=
×
+++
20
2
2
3
2
4
2
5
2
1
log /
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21

MAX11603EEE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 8-Bit 8Ch 188ksps 3.6V Precision ADC
Lifecycle:
New from this manufacturer.
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