MAX11600–MAX11605
Detailed Description
The MAX11600–MAX11605 ADCs use successive-
approximation conversion techniques and input T/H cir-
cuitry to capture and convert an analog signal to a
serial 8-bit digital output. The MAX11600/MAX11601
are 4-channel ADCs, the MAX11602/MAX11603 are
8-channel ADCs and the MAX11604/MAX11605 are
12-channel ADCs. These devices feature a high-speed
2-wire serial interface supporting data rates up to
1.7MHz. Figure 3 shows the simplified functional dia-
gram for the MAX11604/MAX11605.
Power Supply
The MAX11600–MAX11605 operate from a single supply
and consume 350µA at sampling rates up to 188ksps.
The MAX11601/MAX11603/MAX11605 feature a 2.048V
internal reference and the MAX11600/MAX11602/
MAX11604 feature a 4.096V internal reference. All
devices can be configured for use with an external refer-
ence from 1V to V
DD
.
Analog Input and Track/Hold
The MAX11600–MAX11605 analog input architecture
contains an analog input multiplexer (MUX), a T/H
capacitor, T/H switches, a comparator, and a switched
capacitor digital-to-analog converter (DAC) (Figure 4).
In single-ended mode, the analog input multiplexer con-
nects C
T/H
to the analog input selected by CS[3:0] (see
the
Configuration/Setup Bytes (Write Cycle)
section). The
charge on C
T/H
is referenced to GND when converted. In
pseudo-differential mode, the analog input multiplexer
connects C
T/H
to the positive analog input selected by
CS[3:0]. The charge on C
T/H
is referenced to the nega-
tive analog input when converted.
The MAX11600–MAX11605 input configuration is
pseudo-differential in that only the signal at the positive
analog input is sampled with the T/H circuitry. The nega-
tive analog input signal must remain stable within
±0.5 LSB (±0.1 LSB for best results) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from the negative analog input to GND.
See the
Single-Ended/Pseudo-Differential Input
section.
During the acquisition interval, the T/H switches are in
the track position and C
T/H
charges to the analog input
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on C
T/H
as a sample of the input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 8-bit resolution. This action
requires eight conversion clock cycles and is equiva-
lent to transferring a charge of 18pF (V
IN
+ - V
IN
-)
from C
T/H
to the binary weighted capacitive DAC, form-
ing a digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance below 1.5kΩ
does not significantly degrade sampling accuracy. To
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
8 _______________________________________________________________________________________
Analog Input 3/Reference Input/Output. Selected in the setup register
(see Tables 1 and 6).
Reference Input/Output. Selected in the setup register (see Tables 1
and 6).
Analog Input 11/Reference Input/Output. Selected in the setup
register (see Tables 1 and 6).
Positive Supply. Bypass to GND with a 0.1µF capacitor.
