MAX11603EEE+ Datasheet MAX11600EKA+T, MAX11603EEE+, MAX11605EEE+ | P13-P15

Data Byte (Read Cycle)

A read cycle must be initiated to obtain conversion

results. Read cycles begin with the bus master issuing

a START condition followed by 7 address bits and a

read bit (R/W = 1). If the address byte is successfully

received, the MAX11600–MAX11605 (slave) issue an

acknowledge. The master then reads from the slave.

After the master has received the results, it can issue

an acknowledge if it wants to continue reading or a not

acknowledge if it no longer wishes to read. If the

MAX11600–MAX11605 receive a not acknowledge,

they release SDA, allowing the master to generate a

STOP or repeated START. See the

Clock Mode

and

Scan Mode

sections for detailed information on how

data is obtained and converted.

Clock Mode

The clock mode determines the conversion clock, the

acquisition time, and the conversion time. The clock

mode also affects the scan mode. The state of the

setup byte’s CLK bit determines the clock mode (Table

1). At power-up, the MAX11600–MAX11605 default to

internal clock mode (CLK = zero).

Internal Clock

When configured for internal clock mode (CLK = zero),

the MAX11600–MAX11605 use their internal oscillator

as the conversion clock. In internal clock mode, the

MAX11600–MAX11605 begin tracking analog input on

the ninth falling clock edge of a valid slave address

byte. Two internal clock cycles later, the analog signal

is acquired and the conversion begins. While tracking

and converting the analog input signal, the

MAX11600–MAX11605 hold SCL low (clock stretching).

After the conversion completes, the results are stored in

MAX11600–MAX11605

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs

______________________________________________________________________________________ 13

110 1000R/WA

SLAVE ADDRESS

SCL

SDA

123456789

DEVICE SLAVE ADDRESS

1100100

1101101

MAX11600/MAX11601

MAX11602/MAX11603

1100101MAX11604/MAX11605

Figure 7. Slave Address Byte

000 10XXXA

HS MODE MASTER CODE

SCL

SDA

S Sr

F/S MODE HS MODE

Figure 8. F/S Mode to HS Mode Transfer

MAX11600–MAX11605

random access memory (RAM). If the scan mode is set

for multiple conversions, they all happen in succession

with each additional result being stored in RAM. The

MAX11600/MAX11601 contain 8 bytes of RAM, the

MAX11602/MAX11603 contain 8 bytes of RAM, and the

MAX11604/MAX11605 contain 12 bytes of RAM. Once

all conversions are complete, the MAX11600–

MAX11605 release SCL, allowing it to be pulled high.

The master can now clock the results out of the output

shift register at a clock rate of up to 1.7MHz. SCL is

stretched for a maximum acquisition and conversion

time of 7.6µs per channel (Figure 10).

The device RAM contains all of the conversion results

when the MAX11600–MAX11605 release SCL. The con-

verted results are read back in a first-in-first-out (FIFO)

sequence. If AIN_/REF is set to be a reference input or

output (SEL1 = 1, Table 6), AIN_/REF is excluded from

a multichannel scan. This does not apply to the

MAX11602/MAX11603 as each provides separate pins

for AIN7 and REF. RAM contents can be read continu-

ously. If reading continues past the last result stored in

RAM, the pointer wraps around and points to the first

result. Note that only the current conversion results are

read from memory. The device must be addressed with

a read command to obtain new conversion results.

The internal clock mode’s clock stretching quiets the

SCL bus signal, reducing the system noise during con-

version. Using the internal clock also frees the master

(typically a microcontroller) from the burden of running

the conversion clock.

External Clock

When configured for external clock mode (CLK = 1),

the MAX11600–MAX11605 use SCL as the conversion

clock. In external clock mode, the MAX11600–

MAX11605 begin tracking the analog input on the sev-

enth falling clock edge of a valid slave address byte.

One SCL clock cycle later, the analog signal is

acquired and the conversion begins. Unlike internal

clock mode, converted data is available immediately

after the slave-address acknowledge bit. The device

continuously converts input channels dictated by the

scan mode until given a not acknowledge. There is no

need to re-address the device with a read command to

obtain new conversion results (Figure 11).

The conversion must complete in 9ms or droop on the

T/H capacitor degrades conversion results. Use internal

clock mode if the SCL clock period exceeds 1ms.

The MAX11600–MAX11605 must operate in external

clock mode for conversion rates up to 188ksps.

Scan Mode

SCAN0 and SCAN1 of the configuration byte set the

scan-mode configuration. Table 5 shows the scanning

configurations. If AIN_/REF is set to be a reference input

or output (SEL1 = 1, Table 6), AIN_/REF is excluded

from a multichannel scan. This does not apply to the

MAX11602/MAX11603 as each provides separate pins

for AIN7 and REF.

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs

14 ______________________________________________________________________________________

B. 2-BYTE WRITE CYCLE

SLAVE TO MASTER

MASTER TO SLAVE

SLAVE ADDRESS A

711

SETUP OR

CONFIGURATION BYTE

SETUP OR

CONFIGURATION BYTE

P OR Sr

MSB DETERMINES WHETHER

SETUP OR CONFIGURATION BYTE

SLAVE ADDRESS A

711

SETUP OR

CONFIGURATION BYTE

P OR Sr

MSB DETERMINES WHETHER

SETUP OR CONFIGURATION BYTE

A. 1-BYTE WRITE CYCLE

NUMBER OF BITS

Figure 9. Write Cycle

MAX11600–MAX11605

Applications Information

Power-On Reset

The configuration and setup registers (Tables 1 and 2)

default to a single-ended, unipolar, single-channel con-

version on AIN0 using the internal clock with V

as the

reference and AIN_/REF (MAX11600/MAX11601/

MAX11604/MAX11605) configured as an analog input.

For the MAX11602/MAX11603, the REF pin is floating

after power-up. The RAM contents are unknown after

power-up.

Automatic Shutdown

SEL[2:0] of the setup byte (Tables 1 and 6) controls the

state of the reference and AIN_/REF (MAX11600/

MAX11601/MAX11604/MAX11605) or REF (MAX11602/

MAX11603). If automatic shutdown is selected (SEL[2:0] =

100), shutdown occurs between conversions when the

MAX11600–MAX11605 are idle. When operating in exter-

nal clock mode, a STOP condition must be issued to place

the devices in idle mode and benefit from automatic shut-

down. A STOP condition is not necessary in internal clock

mode to benefit from automatic shutdown because power-

down occurs once all contents are written to memory

(Figure 10). All analog circuitry is inactive in shutdown and

supply current is less than 1µA. The digital conversion

results are maintained in RAM during shutdown and are

available for access through the serial interface at any

time prior to a STOP or repeated START condition.

When idle, the MAX11600–MAX11605 wait for a START

condition followed by their slave address (see the

Slave Address

section). Upon reading a valid address

byte, the MAX11600–MAX11605 power up. The analog

circuits do not require any wakeup time from shutdown,

whether using external or internal reference.

Automatic shutdown results in dramatic power savings,

particularly at slow conversion rates. For example, at a

conversion rate of 10ksps, the average supply current

for the MAX1036 is 8µA and drops to 2µA at 1ksps.

At 0.1ksps the average supply current is just 1µA (see

Average Supply Current vs. Conversion Rate in the

Typical Operating Characteristics

section).

Reference Voltage

SEL[2:0] of the setup byte (Table 1) controls the refer-

ence and the AIN_/REF (MAX11600/MAX11601/

MAX11604/MAX11605) or REF (MAX11602/MAX11603)

configuration (Table 6). When AIN_/REF (MAX11600/

MAX11601/MAX11604/MAX11605) is configured to be

a reference input or reference output (SEL1 = 1), con-

versions on AIN_/REF appear as if AIN_/REF is con-

nected to GND (see note 2 of Tables 3 and 4).

Internal Reference

The internal reference is 4.096V for the MAX11600/

MAX11602/MAX11604 and 2.048V for the MAX11601/

MAX11603/MAX11605. SEL1 of the setup byte controls

whether AIN_/REF (MAX11600/MAX11601/MAX11604/

MAX11605) is used for an analog input or a reference

(Table 6). When AIN_/REF (MAX11600/MAX11601/

MAX11604/MAX11605) or REF (MAX11602/MAX11603) is

configured to be an internal reference output (SEL[2:1] =

11), decouple AIN_/REF (MAX11600/MAX11601/

MAX11604/MAX11605) or REF (MAX11602/MAX11603)

to GND with a 0.01µF capacitor. Due to the decoupling

capacitor and the 675Ω reference source impedance,

allow 80µs for the reference to stabilize during initial

power-up. Once powered up, the reference always

remains on until reconfigured. The reference should not

be used to supply current for external circuitry. When the

MAX11602/MAX11603 is in shutdown, the internal refer-

ence output is in a high-impedance state.

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs

______________________________________________________________________________________ 15

BIT 7

(MSB)

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1

BIT 0

(LSB)

REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGL/DIF

BIT NAME DESCRIPTION

7 REG Register bit. 1 = setup byte (Table 1), 0 = configuration byte.

6 SCAN1

5 SCAN0

Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at

power-up.

4 CS3

3 CS2

2 CS1

1 CS0

Channel select bits. Four bits select which analog input channels are to be used for conversion

(Tables 3 and 4). Default to 0000 at power-up. For the MAX11600/MAX11601, CS3 and CS2 are

internally set to 0. For the MAX11602/MAX11603, CS3 is internally set to zero.

0SGL/DIF

1 = single-ended, 0 = pseudo-differential (Tables 3 and 4). Default to 1 at power-up (see the

Single-Ended/Pseudo-Differential Input section).

Table 2. Configuration Byte Format

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

MAX11603EEE+

Mfr. #:

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Description:

Analog to Digital Converters - ADC 8-Bit 8Ch 188ksps 3.6V Precision ADC

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