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ADATE207BBPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
ADATE207
Rev. 0 | Page 9 of 36
Pin No. Mnemonic Input/Output
1
Type Description
G20 DR_EN_CH3_N D, O
Differential
open-drain
Inverted DCL Drive Enable Signal for Channel 3.
L20 LJ_CLK_P D, I
Differential
input
Noninverted Low Jitter Clock Input. This pin
can be multiplexed onto DR_DATA outputs
for Channel 2 and Channel 3.
K19 LJ_CLK_N D, I
Differential
Input
Inverted Low Jitter Clock Input. This pin can
be multiplexed onto DR_DATA outputs for
Channel 2 and Channel 3.
M3 COMP_H_CH0_P D, I
Differential
input
terminated
Noninverted DCL High Comparator Signal for
Channel 0. Differential signal is Logic 1 when
the DUT output is higher than V
OH
.
M2 COMP_H_CH0_N D, I
Differential
input
terminated
Inverted DCL High Comparator Signal for
Channel 0.
J4 COMP_H_CH1_P D, I
Differential
input
terminated
Noninverted DCL High Comparator Signal for
Channel 1. Differential signal is Logic 1 when
the DUT output is higher than V
OH
.
J3 COMP_H_CH1_N D, I
Differential
input
terminated
Inverted DCL High Comparator Signal for
Channel 1.
M18 COMP_H_CH2_P D, I
Differential
input
terminated
Noninverted DCL High Comparator Signal for
Channel 2. Differential signal is Logic 1 when
the DUT output is higher than V
OH
.
M19 COMP_H_CH2_N D, I
Differential
input
terminated
Inverted DCL High Comparator Signal for
Channel 2.
J17 COMP_H_CH3_P D, I
Differential
input
terminated
Noninverted DCL High Comparator Signal for
Channel 3. Differential signal is Logic 1 when
the DUT output is higher than V
OH
.
J18 COMP_H_CH3_N D, I
Differential
input
terminated
Inverted DCL High Comparator Signal for
Channel 3.
L3 COMP_L_CH0_P D, I
Differential
input
terminated
Noninverted DCL Low Comparator Signal for
Channel 0. Differential signal is Logic 1 when
the DUT output is higher than V
OL
.
L4 COMP_L_CH0_N D, I
Differential
input
terminated
Inverted Low Comparator Signal for Channel 0.
H1 COMP_L_CH1_P D, I
Differential
input
terminated
Noninverted DCL Low Comparator Signal for
Channel 1. Differential signal is Logic 1 when
the DUT output is higher than V
OL
.
J2 COMP_L_CH1_N D, I
Differential
input
terminated
Inverted Low Comparator Signal for Channel 1.
L18 COMP_L_CH2_P D, I
Differential
input
terminated
Noninverted DCL Low Comparator Signal for
Channel 2. Differential signal is Logic 1 when
the DUT output is higher than V
OL
.
L17 COMP_L_CH2_N D, I
Differential
Input
terminated
Inverted Low Comparator Signal for Channel 2.
H20 COMP_L_CH3_P D, I
Differential
input
terminated
Noninverted DCL Low Comparator Signal for
Channel 3. Differential signal is Logic 1 when
the DUT output is higher than V
OL
.
J19 COMP_L_CH3_N D, I
Differential
input
terminated
Inverted Low Comparator Signal for Channel 3.
M1 COMP_L_CH0_T A, I, O Analog
Center Tap. Center tap of two 50 Ω resistor
terminations for the low comparator
differential inputs of Channel 0.
ADATE207
Rev. 0 | Page 10 of 36
Pin No. Mnemonic Input/Output
1
Type Description
H2 COMP_L_CH1_T A, I, O Analog
Center Tap. Center tap of two 50 Ω resistor
terminations for the low comparator
differential inputs of Channel 1.
M20 COMP_L_CH2_T A, I, O Analog
Center Tap. Center tap of two 50 Ω resistor
terminations for the low comparator
differential Inputs of Channel 2.
H19 COMP_L_CH3_T A, I, O Analog
Center Tap. Center tap of two 50 Ω resistor
terminations for the low comparator
differential inputs of Channel 3.
M4 COMP_H_CH0_T A, I, O Analog
Center Tap. Center tap of two 50 Ω resistor
terminations for the high comparator
differential inputs of Channel 0.
H3 COMP_H_CH1_T A, I, O Analog
Center Tap. Center tap of two 50 Ω resistor
terminations for the high comparator
differential inputs of Channel 1.
M17 COMP_H_CH2_T A, I, O Analog
Center Tap. Center tap of two 50 Ω resistor
terminations for the high comparator
differential inputs of Channel 2.
H18 COMP_H_CH3_T A, I, O Analog
Center Tap. Center tap of two 50 Ω resistor
terminations for the high comparator
differential inputs of Channel 3.
W15, V15, Y16, W16, Y17,
W17, U16, V17, U18, T17,
U19, U20, T19, T20, R18, R19
CS_AD[15:0] I, O LVCMOS25
Bidirectional Multiplexed Address/Data Bus
for CSR Register Access. Clocked by MCLK.
U13 CS_AS I LVCMOS25
Address Strobe for the Address/Data Bus.
Clocked by MCLK.
V14 CS_RW_B I LVCMOS25
Read/Write Bar Signal for the Address Data
Bus. High for reads. Clocked by MCLK.
Y15 CLKGEN_MD_EN I LVCMOS25
Mode Pin for Clock Generation. Tie to Logic
low for normal operation.
L1 MCLK_P D, I LVCMOS25 Positive Portion of the Master Clock Signal.
K2 MCLK_N D, I LVCMOS25 Negative Portion of the Master Clock Signal.
R4 RESET_B I LVCMOS25 Reset Bar. Active low power-on reset signal.
D19 TDI I LVCMOS25
Scan Chain Data In. Tie to Logic high for
normal operation.
C8 TDO O LVCMOS25 Scan Chain Data Out.
A7 TCK I LVCMOS25
Scan Chain Clock. Tie to Logic high for
normal operation.
D18 TMS I LVCMOS25
Scan Chain Mode. Tie to Logic high for
normal operation.
E17 TRST_B I LVCMOS25
Active Low Scan Chain Reset. Tie to Logic low
for normal operation.
R1 REF_1K A, I, O Analog
Controls the output current of the differential
open drain outputs.
P3 T_DIODE A, I, O Analog
Thermal Sensing Diode Anode. Force current
and measure voltage to measure die
temperature stability.
T2 TESTMODE I LVCMOS25 Must be connected to VSS.
F2, F1, F19, F20, T1, R3, R2,
R20, N4, N17, P18
NC No Connect. Must be left unconnected.
SHIELD A, I, O, P GND Connect to VSS.
R17, U15, D9, D11, D12, D13,
U10, U9, V7, V5
IOVSS P GND Power, 0.0 V.
U8, U6, T18, V16 IOVDD P VDD Power, 2.5 V.
C9, C11, C13, C15, V11, V9 IOVDD P Power, 2.5 V.
A3 to A1 VSS P Power, 0.0 V
ADATE207
Rev. 0 | Page 11 of 36
Pin No. Mnemonic Input/Output
1
Type Description
Y20 to Y18, Y12, Y11, Y8, Y3 to
Y1, W20, W1, V20, V1, N20, N1,
K20, K1, J20, J1, C20, C1, B20,
B1, A20 to A18, A13, A10, A9
VSS P GND Power, 0.0 V.
W19, W18, W3, W2, V19, V18,
V3, V2, U17, U14, U11, U7, U4,
P17, P4, K17, K4, G17, G4,
D17, D14, D10, D7, D4, C19,
C18, C3, C2, B19, B18, B3, B2
VDD P VDD Power, 2.5 V.
1
A = analog, D = differential, I = input, O = output, P = power.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

ADATE207BBPZ

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Manufacturer:
Analog Devices Inc.
Description:
Clock Generators & Support Products Quad Pin Timing Formatter
Lifecycle:
New from this manufacturer.
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