ADATE207
Rev. 0 | Page 19 of 36
MCLK
CYCLES
RD3 A4 WD4
CS_AS
CS_RW_B
CS_AD
A1 WD1 A2 WD2 A3
1 CYCLE OF BUS TURN-AROUND + 8 CYCLES OF READ DATA DELAY
1 CYCLE OF BUS TURN-AROUND
ASSERTED FOR 2 OR MORE CYCLES WILL ALLOW
1 EXTRA CYCLE OF READ DATA HOLD ON BUS
(OPTIONAL)
05557-010
Figure 16. Bus Interface Function Timing Diagram
Figure 16 shows the bus functional timing while performing
both read and write operations. Highlights include
• The bus implements a synchronous protocol, where read
and write transactions are slotted into MCLK cycles.
• The CS_AD bus lines, 2.5 V CMOS signals, can be tri-
stated. To implement a multidrop bus, strict adherence to
proper bus turnaround from reads to writes (and vice
versa) is required.
• The initial bus turn around time for a read operation is
indicative of the internal path length inside the
ADATE207.
• After accepting a read transaction, the ADATE207 waits
one MCLK cycle for bus turnaround, and then turns on its
bus drivers to precharge the bus.
• There must be at least one MCLK cycle between a read
followed by a write transaction, and between the address
and read data cycles due to bus turnaround. The ADATE207
tristates the bus on the MCLK after it has finished driving
the read data.
• A write transaction can be followed immediately by a read
transaction. Likewise, a series of write transactions can be
grouped together with no dead time in between transactions.
• To ease board timing, holding the CS_RW_B signal high
allows the read data to stay on the bus one extra MCLK
cycle. One application allows two clock cycles for read data
to propagate to its destination. Note that holding CS_RW_B
high for more that two cycles has no effect.
All external bus signals come into the ADATE207 and are
registered by the MCLK. Then, the registered signals are used
to interface to the four channel-specific register banks and the
common block. Each register bank receives an address, data, the
read/write signal, and a block select. Even though some portions
of the internal timing circuitry run at a high rate than the
master clock, all of the register blocks run at the master clock,
MCLK, rate.
When a block is selected, a read or write operation is performed.
For read operations, data is enabled onto the read data bus of a
block, and that data is OR’ed with four other block-specific
RDATA busses to form the read data that is sent from the
ADATE207. Note that the read data takes more than one clock
cycle. The bus interface state machine controls the output
enable accordingly.
The write data is reregistered (retimed) to require only one
MCLK cycle to write the data into the targeted register (or
registers, in the case where multiple channels are selected).
Burst Mode
Burst mode is a special mode that allows for successive reads or
writes with a predetermined addressing scheme.
Figure 17
shows the burst mode operation of the bus. The primary
purpose of burst mode is to allow fast writes into the waveform
memory for each channel. Burst mode is initiated and completely
controlled via the bus interface pins of the ADATE207.
Burst mode is initiated with a special address cycle, as defined
in
Tabl e 12. Burst mode cycles are shown in Figure 17 through
Figure 19 and incorporate the following conditions:
• The completion of burst mode is controlled by the address
strobe signal. If address strobe is deasserted in a particular
MCLK cycle, that becomes the last cycle of the burst.
• Only a series of burst writes or reads can occur. There can
be no mixing of reads and writes in a burst sequence.
• The bus interface state machine takes over the internal
register address only and the read/write selection signal.
• The CSR blocks and channel-specific memory accesses
operate the same in burst mode as they do in the normal
read/write transactions.
• There must be at least two MCLK cycles between a read
burst followed by another read or write transaction, and
between the address and read data cycles due to bus turn-
around. The ADATE207 tristates the bus on the MCLK
after it is finished driving read data, as shown in
Figure 18.
• When extended read data hold mode is selected during a
read burst, the internal address bus increments every other
cycle, causing read data on the CS_AD bus to change every
other cycle, as shown in
Figure 19.
