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ADATE207BBPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
ADATE207
Rev. 0 | Page 30 of 36
Position Description Reset State
Bits[10:08]
PAT_DUTDATA2 Select. A binary encoded data field that selects which edge and which comparator
to drive out of the ADATE207 PAT_DUTDATAx[2] pin.
0x0
0x0 = Edge D0 low comparator.
0x1 = Edge D0 high comparator.
0x2 = Edge D1 low comparator.
0x3 = Edge D1 high comparator.
0x4 = Edge D2 low comparator.
0x5 = Edge D2 high comparator.
0x6 = Edge D3 low comparator.
0x7 = Edge D3 high comparator.
Bit 07 Not Used 0
Bits[06:04]
PAT_DUTDATA1 Select. A binary encoded data field that selects which edge and which comparator
to drive out of the ADATE207 PAT_DUTDATAx[1] pin.
0x0
0x0 = Edge D0 low comparator.
0x1 = Edge D0 high comparator.
0x2 = Edge D1 low comparator.
0x3 = Edge D1 high comparator.
0x4 = Edge D2 low comparator.
0x5 = Edge D2 high comparator.
0x6 = Edge D3 low comparator.
0x7 = Edge D3 high comparator.
Bit 03 Not Used 0
Bits[02:00]
PAT_DUTDATA0 Select. A binary encoded data field that selects which edge and which comparator
to drive out of the ADATE207 PAT_DUTDATAx[0] pin.
0x0
0x0 = Edge D0 low comparator.
0x1 = Edge D0 high comparator.
0x2 = Edge D1 low comparator.
0x3 = Edge D1 high comparator.
0x4 = Edge D2 low comparator.
0x5 = Edge D2 high comparator.
0x6 = Edge D3 low comparator.
0x7 = Edge D3 high comparator.
CHIP-SPECIFIC (COMMON) REGISTERS
Name: Software Resets
Address: 0x19
Type: Write
Table 33. Software Resets
Position Description Reset State
Bit 15 DLL Ready. Indicates that the internal PLL and DLL are stable after a reset and/or MCLK change. Dynamic
Bits[14:04] Not Used. 0x000
Bit 03 Error Registers Clear. 0x0
Writing a 1 to this bit creates a pulse to clear all the delay generation errors for all channels and
resets the edge generation logic.
Writing a 0 has no affect.
Bit 02 Accumulated Fail Registers Clear. 0x0
Writing a 1 to this bit creates a pulse to clear the accumulated fail registers for all channels.
Writing a 0 has no affect.
ADATE207
Rev. 0 | Page 31 of 36
Position Description Reset State
Bit 01 Fail Counters Clear. 0x0
Writing a 1 to this bit creates a pulse to clear the fail counters for all channels.
Writing a 0 has no affect.
Bit 00
Soft Reset. Writing this register bit to a Logic 1 causes the ADATE207 to generate a software reset. This
is logically equivalent to a hard reset via the I_RESET_B pin. All logic and registers
are reset.
0x0
Name: Round Trip Delay Value
Address: 0x1A
Type: Read/Write
Table 34. Round Trip Delay Value
Position Description Reset State
Bits[15:05] Not Used. 0x000
Bits[4:00]
Round Trip Delay Value. Programs the round-trip delay from the ADATE207 drive to compare pins, in
units of 2.5 ns. The maximum delay is 80 ns (value = 31) and the minimum delay is 2.5 ns (value = 0).
0x0
Name: T0 Alignment Pipeline Depth
Address: 0x1B
Type: Read/Write
Table 35. T0 Alignment Pipeline Depth
Position Description Reset State
Bits[15:05] Not Used. 0x000
Bits[04:00]
T0 Alignment Pipeline Depth. This pipeline value matches the edge generation delay for compare
edges thereby correctly aligning compare fails and DUT data to the T0 pipeline. It should be
programmed no higher than 30 and ≥ 10.5+ RTD/4.
0x0
TMU Channel Select
This register selects one of four channels to independently direct to the TMU arm, start, and stop buses.
Name: TMU Channel Select
Address: 0x1C
Type: Read/Write
Table 36. TMU Channel Select
Position Description Reset State
Bits[15:12] Not Used. 0x00
Bit 11 TMU Stop Enable. A zero tristates the TMU stop output. 0
Bits[10:08] TMU Stop, Channel Select Multiplexer. A binary encoded data field. 0x00
0x0 selects Channel 0 comparator high.
0x1 selects Channel 0 comparator low.
0x2 selects Channel 1 comparator high.
0x3 selects Channel 1 comparator low.
0x4 selects Channel 2 comparator high.
0x5 selects Channel 2 comparator low.
0x6 selects Channel 3 comparator high.
0x7 selects Channel 3 comparator low.
Bit 07 TMU Start Enable. A zero tristates the TMU stop output. 0
Bits[06:04] TMU Start, Channel Select Multiplexer. A binary encoded data field. 0x00
ADATE207
Rev. 0 | Page 32 of 36
Position Description Reset State
0x0 selects Channel 0 comparator high.
0x1 selects Channel 0 comparator low.
0x2 selects Channel 1 comparator high.
0x3 selects Channel 1 comparator low.
0x4 selects Channel 2 comparator high.
0x5 selects Channel 2 comparator low.
0x6 selects Channel 3 comparator high.
0x7 selects Channel 3 comparator low.
Bit 03 TMU Arm Enable. A zero tristates the TMU Stop output. 0
Bits[02:00] TMU Arm Channel Select Multiplexer. A binary encoded data field. 0x00
0x0 selects Channel 0 comparator high.
0x1 selects Channel 0 comparator low.
0x2 selects Channel 1 comparator high.
0x3 selects Channel 1 comparator low.
0x4 selects Channel 2 comparator high.
0x5 selects Channel 2 comparator low.
0x6 selects Channel 3 comparator high.
0x7 selects Channel 3 comparator low.
Name: Channel Multiplex Enable
Address: 0x1D
Type: Read/Write
Table 37. Channel Multiplex Enable
Position Description Reset State
Bits[15:02] Not Used. 0x0000
Bit 01
CH2 Multiplex Enable. This channel can be 2-way multiplexed. Setting this bit to 1 enables Channel 3
to be multiplexed on Channel 2.
0
Bit 00
CH0 Multiplex Enable. This channel can be 2-way multiplexed. Setting this bit to 1 enables Channel 1
to be multiplexed on Channel 0.
0
Name: Channel Status
Address: 0x1E
Type: Read
Table 38. Channel Status
Position Description Reset State
Bit 15
Channel 3 Failure. This indicates that the channel had a failure. This signal is the Logic OR of the
accumulated fail registers (AFRs) of the channel. More details of the fail can be found by reading the
AFRs or fail counter for Channel 3.
0x0
Bit 14
Channel 2 Failure. This indicates that the channel had a failure. This signal is the Logic OR of the
accumulated fail registers (AFRs) of the channel. More details of the fail can be found by reading the
AFRs or fail counter for Channel 2.
0x0
Bit 13
Channel 1 Failure. This indicates that the channel had a failure. This signal is the Logic OR of the
accumulated fail registers (AFRs) of the channel. More details of the fail can be found by reading the
AFRs or fail counter for Channel 1.
0x0
Bit 12
Channel 0 Failure. This indicates that the channel had a failure. This signal is the Logic OR of the
accumulated fail registers (AFRs) of the channel. More details of the fail can be found by reading the
AFRs or fail counter for Channel 0.
0x0
Bit 11
Channel 3 Timing Error. This indicates that the channel had a timing error. This signal is the Logic OR of
the timing error flags of the channel. More details of the error can be found by reading the error flags
for Channel 3.
0x0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

ADATE207BBPZ

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Manufacturer:
Analog Devices Inc.
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Clock Generators & Support Products Quad Pin Timing Formatter
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