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ADATE207BBPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
ADATE207
Rev. 0 | Page 3 of 36
SPECIFICATIONS
DC SPECIFICATIONS
T
C
= 85°C ± 5°C, VDD = 2.5 V, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
POWER SUPPLY
Operating Supply Current, IDD All channels repeating pattern of 1/H/0/L across
D0/D1/D2/D3 edges every 20 ns
2.5 2.7 A
Power Dissipation
1
All channels repeating pattern of 1/H/0/L across
D0/D1/D2/D3 edges every 20 ns
6.3 7.1 W
All channels repeating pattern of H/L/H/L across
D0/D1/D2/D3 edges every 10 ns
6.85 W
Idle mode; no patterns bursting 5.7 W
Operating Supply Current, IDD All channels repeating pattern of 1/0/1/0 across
D0/D1/D2/D3 edges every 10 ns
2.7 A
Idle mode; no patterns bursting 2.2 A
DIGITAL INPUTS
LVCMOS25
V
IL
0.7 V
I
IL
V
IL
= 0 V 1 μA
V
IH
1.7 V
I
IH
V
IH
= 2.5 V 1 μA
Pin Capacitance Guaranteed by simulation 3.5 pF
Differential Inputs with Internal
Termination
V
DIFF
200 mV
Input Voltage Range 1.0 VDD V
Differential inputs with External
Termination
V
DIFF
200 mV
Input Voltage Range 1.0 VDD V
R Termination 50 ± 15% Ω
DIGITAL BIDIRECTIONALS
LVCMOS25
V
IL
0.7 V
I
IL
V
IL
= 0 V 1 μA
V
IH
1.7 V
I
IH
V
IH
= 2.5 V 1 μA
DIGITAL OUTPUTS
LVCMOS25
V
OL
I
OL
= 8 mA 0.4 V
V
OH
I
OH
= 8 mA VDD − 0.4 V
Open Drain Differential Outputs REF_1K > 100 kΩ to GND
V
DIFF
V
TERM
= 50 Ω to VDD 200 300 mV
V
OL
(Individual Leg of Pair) V
TERM
= 50 Ω to VDD 2.49 V
V
OH
(Individual Leg of Pair) V
TERM
= 50 Ω to VDD 2.2 V
Ambient Potential I
DIODE
= 100 μA 715 mV
Operating Potential I
DIODE
= 100 μA 600 630 mV
Temperature Coefficient I
DIODE
= 100 μA 1.4 mV/°C
1
Power dissipation specifically indicates part dissipation and does not include power dissipated in external terminations.
ADATE207
Rev. 0 | Page 4 of 36
AC SPECIFICATIONS
T
C
= 85°C ± 5°C, VDD = 2.5 V, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
CLOCK INPUTS
Master Clock (MCLK) Frequency 100 MHz
MCLK Duty Cycle 46 50 54 %
DRIVE OUTPUTS
Output Pulse Width Timing error < ±125 ps 1 ns
COMPARE INPUTS
Minimum Comparison Window Width 1.25 ns
Minimum Detectable Glitch Width 1.25 ns
EDGE PERFORMANCE
Retrigger Time 2.5 ns
Edge Delay 0
Lesser of 4 T0 cycles
or 163.8 μs
Vernier Resolution 39.06 ps
Vernier Timing DNL −150 +150 ps
Vernier Timing INL −150 +150 ps
Vernier Temperature Coefficient 4 ps/°C
Edge Jitter MCLK jitter 5 ps rms 20 ps rms
CONTROL AND STATUS REGISTER (CSR) INTERFACE
Clock Period 10 ns
Setup Time (t
BSU
) MCLK 1.1 ns
Hold Time (t
BH
) MCLK 0.5 ns
Clock to Output (t
BCO
) MCLK 2.5 7.0 ns
Clock to Tristate (t
BCZ
) 2.3 4.2 ns
Clock to Data Valid from Tristate (t
BCZV
) 0 7.0 ns
DIGITAL INPUTS
Set Up (t
ISU
) MCLK 1.7 ns
Hold Time (t
IH
) MCLK 0.5 ns
DIGITAL OUTPUTS
Clock to Output (t
OCO
) MCLK 0.7 1.6 ns
JTAG PORTS
JTAG Clock Period 100 ns
Setup Time (t
SSU
) JTAG CLOCK 50 ns
Hold Time (t
SH
) JTAG CLOCK 50 ns
Clock to Output (t
SCO
) JTAG CLOCK 50 ns
ADATE207
Rev. 0 | Page 5 of 36
TIMING DIAGRAMS
t
ISU
t
IH
MCLK_P
DIGITAL INPUTS
MCLK_N
DIGITAL OUTPUTS
t
OCO(MIN)
t
OCO(MAX)
05557-007
Figure 2. Timing Diagram for Inputs and Outputs
t
JSU
t
JH
JTAG
JTAG INPUT
JTAG OUTPU
T
t
JCO
05557-015
Figure 3. Timing Diagram for Scan Inputs and Scan Outputs
t
BSU
t
BH
MCLK_P
BIDIRECTIONAL (WRITES)
MCLK_N
BIDIRECTIONAL (READS)
t
BCO(MIN)
t
BCO(MAX)
t
BCZ
t
BCZV
05557-008
Figure 4. Timing Diagram for Bidirectional Reads and Writes
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

ADATE207BBPZ

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Buy ADATE207BBPZ
Manufacturer:
Analog Devices Inc.
Description:
Clock Generators & Support Products Quad Pin Timing Formatter
Lifecycle:
New from this manufacturer.
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