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ADATE207BBPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
ADATE207
Rev. 0 | Page 6 of 36
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VDD −0.3 V to +2.8 V
Digital Inputs −0.3 V to VDD + 0.3 V
Resistor Termination pins −0.3 to VDD + 0.3 V
Resistor Termination Current 12 mA max
Termination Pad Current 12 mA max
Junction Temperature 125°C
Storage Temperature −40 to 125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4. Recommended Operating/Environmental
Conditions
Parameter Min Typ Max Unit
VDD 2.375 2.5 2.625 V
Case Temperature (T
C
) 85 °C
Relative Humidity
(Noncondensing)
85 %
THERMAL RESISTANCE
Table 5. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
256-Lead BGA_ED 1.5 °C/W
In Still Air 14.3 °C/W
200 LFPM 12.0 °C/W
400 LFPM 11.2 °C/W
BYPASSING SCHEME
For decoupling, best practice suggests that to preserve as much
of the plane-to-plane capacitance as possible, do not perforate
the planes for VSS and VDD. Secondly, it is advisable to decouple
VDD to VSS by using 0.1 μF high frequency ceramic capacitors.
The trace to the capacitor should be kept to an absolute minimum
length. It is recommend that one capacitor be placed in the
corner of the chip and one in the middle of each side for a total
of eight capacitors for VDD to VSS. Furthermore, decouple
IOVDD to IOVSS on each side of the device. It is recommended
that 10 μF tantalum or ceramic capacitors be used for low
frequency decoupling around the device. It is not important for
these capacitors to be close to the device.
Table 6. Data Table for 256-Lead Ball Grid Array, Thermally
Enhanced, 27 mm × 27 mm Body
Dimension
Minimum
(mm)
Nominal
(mm)
Maximum
(mm)
A
1.70
A1 0.50 0.60 0.70
A2 0.60 0.80 1.00
D 26.90 27.00 27.10
D1 24.03 24.13 24.23
E 26.90 27.00 27.10
E1 24.03 24.13 24.23
b 0.60 0.75 0.90
e
1.27
aaa
0.20
bbb
0.25
ccc
0.35
ddd
0.20
eee
0.30
fff
0.15
S
0.635
ESD CAUTION
ADATE207
Rev. 0 | Page 7 of 36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADATE207
PATTERN DATA
PERIOD DATA
COMPARE FAILS
RECEIVE DATA
CH3 DCL I/F
CH2 DCL I/F
CH1 DCL I/F
CH0 DCL I/F
COMMAND/
STATUS BUS
TIME
MEASUREMENT
05557-009
Figure 5. Connection Overview Diagram
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
2468101214161820
135791113151719
BOTTOM
VIEW
(Not to Scale)
ADATE207
05557-014
Figure 6. Ball Grid Array
Table 7. Pin Function Descriptions
Pin No. Mnemonic Input/Output
1
Type Description
B4, A4, C5, D6 PAT_MASK[3:0] I LVCMOS25
Mask Failures. Used to mask failures on D3,
D2, D1 and D0 edges, respectively. Clocked
by MCLK.
T3, U1, U2, T4, U3, V4, U5, W4 PAT_PATDATA_0[7:0] I LVCMOS25
Channel 0 Waveform Memory Address. Use
these pins to address waveform memory for
Channel 0. Clocked by MCLK.
B5, A5, C6, B6, A6, C7, B7, D8 PAT_PATDATA_1[7:0] I LVCMOS25
Channel 1 Waveform Memory Address. Use
these pins to address waveform memory for
Channel 1. Clocked by MCLK.
W212, V12, Y13, U12, W13,
V13, Y14, W14
PAT_PATDATA_2[7:0] I LVCMOS25
Channel 2 Waveform Memory Address. Use
these pins to address waveform memory for
Channel 2. Clocked by MCLK.
A16, B16, D15, C16, A17,
B17, D16, C17
PAT_PATDATA_3[7:0] I LVCMOS25
Channel 3 Waveform Memory Address. Use
these pins to address waveform memory for
Channel 3. Clocked by MCLK.
Y4, W5, V6 PAT_FAIL_0[3:0] O LVCMOS25
Fails on D3, D2, D1 and D0 Edges for Channel 0.
Clocked by MCLK.
B8, A8, B9, B10 PAT_FAIL_1[3:0] O LVCMOS25
Fails on D3, D2, D1 and D0 Edges for Channel 1.
Clocked by MCLK.
V8, W8, W9, Y9 PAT_FAIL_2[3:0] O LVCMOS25
Fails on D3, D2, D1 and D0 Edges for Channel 2.
Clocked by MCLK.
B12, C12, B13, A14 PAT_FAIL_3[3:0] O LVCMOS25
Fails on D3, D2, D1 and D0 Edges for Channel 3.
Clocked by MCLK.
W6, Y6, W7, Y7 PAT_DUTDATA_0[3:0] O LVCMOS25
DUT Capture Data from Channel 0. Clocked
by MCLK.
C10, A11, B11, A12 PAT_DUTDATA_1[3:0] O LVCMOS25
DUT Capture Data from Channel 1. Clocked
by MCLK.
V10, W10, Y10, W11 PAT_DUTDATA_2[3:0] O LVCMOS25
DUT Capture Data from Channel 2. Clocked
by MCLK.
B14, C14, A15, B15 PAT_DUTDATA_3[3:0] O LVCMOS25
DUT Capture Data from Channel 3. Clocked
by MCLK.
ADATE207
Rev. 0 | Page 8 of 36
Pin No. Mnemonic Input/Output
1
Type Description
D5 PAT_DATA_VALID I LVCMOS25
Indicates Pattern Bursting. When not
asserted, edges are disabled and the drive
and expect signals are static. Clocked by
MCLK.
F3 PER_EARLY_T0EN I LVCMOS25
Indicates the Start of a T0 Period. Clocked
by MCLK.
E1 PER_EARLY_C0EN I LVCMOS25
Indicates the Start of a C0 Period. Clocked
by MCLK.
C4, D3, E4, D2, D1, E3, F4, E2 INPUT_DELAY[7:0] I LVCMOS25
Global Delay Input For All Edges. Clocked
by MCLK.
F18 TMU_ARM_P D, O
Differential
open-drain
Differential Tristate Output. Noninverted TMU
ARM multiplexer output. High-Z when not
enabled.
E20 TMU_ARM_N D, O
Differential
open-drain
Differential Tristate Output. Inverted TMU
ARM multiplexer output. High-Z when not
enabled.
E19 TMU_START_P D, O
Differential
open-drain
Differential Tristate Output. Noninverted TMU
START multiplexer output. High-Z when not
enabled.
F17 TMU_START_N D, O
Differential
open-drain
Differential Tristate Output. Inverted TMU
START multiplexer output. High-Z when not
enabled.
E18 TMU_STOP_P D, O
Differential
open-drain
Noninverted TMU STOP Multiplexer Output.
Differential tristate output. High-Z when not
enabled.
D20 TMU_STOP_N D, O
Differential
open-drain
Inverted TMU STOP Multiplexer Output.
Differential tristate output. High-Z when not
enabled.
P2 DR_DATA_CH0_P D, O
Differential
open-drain
Noninverted DCL Drive Data Signal for
Channel 0.
P1 DR_DATA_CH0_N D, O
Differential
open-drain
Inverted DCL Drive Data Signal for Channel 0.
G3 DR_DATA_CH1_P D, O
Differential
open-drain
Noninverted DCL Drive Data Signal for
Channel 1.
H4 DR_DATA_CH1_N D, O
Differential
open-drain
Inverted DCL Drive Data Signal for Channel 1.
P19 DR_DATA_CH2_P D, O
Differential
open-drain
Noninverted DCL Drive Data Signal for
Channel 2.
P20 DR_DATA_CH2_N DO
Differential
open-drain
Inverted DCL Drive Data Signal for Channel 2.
G18 DR_DATA_CH3_P D, O
Differential
open-drain
Noninverted DCL Drive Data Signal for
Channel 3.
H17 DR_DATA_CH3_N D, O
Differential
open-drain
Inverted DCL Drive Data Signal for Channel 3.
N3 DR_EN_CH0_P D, O
Differential
open-drain
Noninverted DCL Drive Enable Signal for
Channel 0.
N2 DR_EN_CH0_N D, O
Differential
open-drain
Inverted DCL Drive Enable Signal for Channel 0.
G2 DR_EN_CH1_P D, O
Differential
open-drain
Noninverted DCL Drive Enable Signal for
Channel 1.
G1 DR_EN_CH1_N D, O
Differential
open-drain
Inverted DCL Drive Enable Signal for Channel 1.
N18 DR_EN_CH2_P D, O
Differential
open-drain
Noninverted DCL Drive Enable Signal for
Channel 2.
N19 DR_EN_CH2_N D, O
Differential
open-drain
Inverted DCL Drive Enable Signal for Channel 2.
G19 DR_EN_CH3_P D, O
Differential
open-drain
Noninverted DCL Drive Enable Signal for
Channel 3.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

ADATE207BBPZ

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Manufacturer:
Analog Devices Inc.
Description:
Clock Generators & Support Products Quad Pin Timing Formatter
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