ADATE207BBPZ Datasheet ADATE207BBPZ | P13-P15

ADATE207

Rev. 0 | Page 12 of 36

THEORY OF OPERATION

WAVEFORM MEMORY

Pattern data is used to address the waveform memory and is

eight bits wide per channel, supporting 256 unique waveforms.

The data width of the waveform memory is 26 bits wide per

event or 104 bits wide per pin. The waveform memory data bits

are partitioned into two fields, a 22-bit wide delay field, and a

4-bit event code field. The waveform memory is dual port

allowing CPU access during pattern bursting.

Pattern data is used as a pointer to one of the defined 256

waveforms, and can be partitioned into vector data and a time

set pointer. Using three bits of vector data for the pin state, the

other five bits can be used as 32 possible time sets. Supporting

dual I/O per cycle, two sets of 3-bit vector data can be used in

combination with two bits of a time set pointer providing four

possible time sets. A straightforward trade off in time sets vs.

device vectors per tester cycle is possible.

Pattern data is qualified with the input signal PAT_DATA_VALID.

When asserted, the pattern data is evaluated. When not asserted,

events and timing edges are disabled and the input pattern data

is ignored.

EVENT GENERATORS

Each channel has four programmable event generators. Each

event generator inputs a delay, an event code from the waveform

memory, and an 8-bit INPUT_DELAY. The waveform delay and

the 8-bit INPUT_DELAY combine to produce programmable

delays from T0 cycle starts. Each programmable delay can span

up to 4 T0 periods and up to 163 μs with a nominal delay reso-

lution of 39.06 ps. There are 16 possible events. These events are

compatible with STIL waveform events, as shown in

Table 8, to

create all of the conventional drive and compare formats.

There is a programmable pipeline delay with 2.5 ns resolution

between the drive events and the compare events allowing for

round trip delay (RTD) compensation.

DELAY GENERATION

Each of the four events per channel has an independent delay

generator (D0, D1, D2, and D3). Each delay generator triggers

from a period start using either T0 or C0 periods. A delay value

is the sum of three values: the user programmed delay that is

programmed in waveform memory, a calibration delay indexed

by the selected event, and a global INPUT_DELAY signal that is

used across all channels. These delays are summed and triggered

from the selected period start. The delays are generated using

counts of 2.5 ns plus a 6-bit analog vernier delay. The analog

vernier delay is expressed as a binary fractional value of 2.5 ns.

Table 8. STIL-Compatible Events

Code Action Description

N No action Default.

0 Drive low Sets driver to low state.

1 Drive high Sets driver to high state.

Z Force off

Disables the driver and enable

the load.

U Force up

Force Logic high. Enables the

driver and disables the load.

D Force down

Force Logic low. Enables the

driver and disables the load.

P Force prior Enable the driver.

L Compare low Edge compare low.

H Compare high Edge compare high.

Compare

unknown

Don’t care. Can be used to close

window compare.

T Compare off Edge compare midband.

V Compare valid Edge compare valid logic level.

Compare low

window

Start window compare against

Logic low.

Compare high

window

Start window compare against

Logic high.

Compare off

window

Start window compare against

midband.

Compare valid

window

Start window compare for valid

logic level.

The delay generator uses a value expressed as the binary value

bbbbbbbbbbbbbbbb.vvvvvv where there are 16 bits (b) left of

the binary point and 6 bits (v) right of the binary point. The

b bits represent an integer number of counts of 2.5 ns and the

v bits represent a fractional value of 2.5 ns with a resolution of

2.5 ns/64 or 39.06 ps.

VERNIER RESOLUTION

The analog vernier delays are implemented using a modulo 60

algorithm and dividing 2.5 ns into 60 even parts. Because the

delays are expressed using a binary representation, an internal

mapping algorithm generates the delays. Ignoring analog timing

errors, the actual delay produced for the six bits of vernier value

(vvvvvv) is expressed as

Delay = (2.5 ns/60) × INT (.5 + (vvvvvv × 60/64))

This mapping results in an inherent discontinuity in the

linearity curve.

Figure 7 shows the linearity of a typical vernier. On certain

delay codes, the vernier exhibits non-monotonicity. To obtain a

monotonic delay curve, these code jumps should be ignored by

the user.

ADATE207

Rev. 0 | Page 13 of 36

2.5

2.0

1.5

1.0

0.5

10 20 30 40 50 60

TYPICAL VERNIER

05557-016

DELAY CODE

(ns)

Figure 7. Delay Curve of a Typical Vernier

DRIVE AND COMPARE LOGIC

The drive logic consists of two high speed differential reset/set

flip flops controlling the drive data and drive enable signals.

They are controlled from the four events per channel, enabled

via decode of the event code. In addition, the flip flops can be

controlled from an adjacent channel event in a multiplex mode.

The four-channel device can be multiplexed such that there are

either four pins with four events each, or two pins with eight

events each.

The compare logic supports dual level comparators for voltage

comparisons against V

and V

levels. The comparator outputs

are checked against four possible states, low (less than V

), high

(greater than V

), off or midband (between V

and V

), and

valid (either above V

or below V

). The high comparator

inputs (COMP_H) are Logic 1 when the DUT output is greater

than V

. The low comparator inputs (COMP_L) are Logic 1

when the DUT output is greater than V

The compare logic supports both single edge and window com-

parisons and can support up to four comparisons per cycle using

the four events. Each comparison can generate a fail, accumulating

per pin with individual fail counters. Fail outputs are resynchro-

nized to T0 and output for fail processing.

Fails can be masked on a per edge basis and match mode is

supported. Masking of failures prevents incrementing of the fail

counter and the setting of the accumulated fail registers. It does

not prevent the fail signals from reflecting the comparison state

of the expect edge. Strobe comparison fails are associated with

the timing edge that generates the strobe.

A pair of timing edges can be used to create a window of time

over which to check the DUT output levels. Timing Edge D0

and Timing Edge D1 form a window with D0 opening the

window and D1 closing the window. Timing Edge D2 and

Timing Edge D3 are similarly employed for window

comparisons. Window comparison fails are associated with the

timing edge that generates the window close strobe. Window

failures only come out on D1 or D3 edges.

Tabl e 9 shows the

relationship between the edges on which the fails are detected

and the bit position on the PAT_FAIL pins.

Table 9. Edge and Window Fail Bit Descriptions

Bit Fail

Description

Fail

Mask Bit

3 PAT_FAIL_x[3]

Edge D3 Fail and Window

D2/D3 Fail

PAT_MASK[3]

2 PAT_FAIL_x[2] Edge D2 Fail PAT_MASK[2]

1 PAT_FAIL_x[1]

Edge D1 Fail and Window

D0/D1 Fail

PAT_MASK[1]

0 PAT_FAIL_x[0] Edge D0 Fail PAT_MASK[0]

PAT_FAIL_x refers to Channel 0 to Channel 3.

PAT_MASK inputs mask failures across the channels for four

possible edges. Asserting PAT_MASK[0] masks failures for

Timing Edge D0. When failures are masked, the accumulated fail

PAT_FAIL_x outputs remain asserted if the expected vector is

not seen allowing for match mode applications.

ADATE207

Rev. 0 | Page 14 of 36

T0 M C

M M

T0 M

INPUT_DELAY

44 11

PROGRAMMABLE

RTD DELAY [0:31]

DUT

FIFO

PROGRAMMABLE

T0 DELAY [0:30]

PAT_PATDAT

FAIL

DUTDATA

LEGEND

RTD COMPENSATION

CLK400

PIPELINE

MCLK

PIPELINE

05557-002

Figure 8. Pipeline Diagram

Dual comparator inputs of the even channels (0 and 2) are

routed to the compare logic of adjacent channels to provide

×2 multiplexing. In ×2 multiplexing, Pin 0 and Pin 2 comparator

inputs route to Pin 1 and Pin 3, respectively, providing up to

eight compare events per cycle on the multiplexed channels.

PIPELINE CONSIDERATIONS

For proper functionality, drive actions, compare events, and fail

accumulation mask requirements need to be coordinated within

the device by adjusting the internal delay paths. The ADATE207

provides two programmable delay paths, the RTD pipeline and

the T0 alignment pipeline, as shown in

Figure 8. The pattern

input and output signals are synchronous with the MCLK and

pipelined on T0 periods.

Figure 8 shows the pipeline diagram of the ADATE207. The T0

delay pipeline is programmable. It must be sufficiently deep to

cover the round trip delay compensation, yet no deeper than

the FIFO depth of the fail logic.

The minimum T0 alignment pipeline depth needed is

dependent on the programmed RTD compensation. The

programmed T0 alignment pipeline depth must conform to the

values listed in

Tabl e 10. The maximum number of 30 can be

used in any circumstance. Depending upon the MCLK rate and

the programmed RTD compensation, a smaller pipeline depth

can be used.

Table 10. T0 Pipeline Requirements

T0 Alignment Pipelines

Minimum Maximum

10.5 + RTD/4 30

MCLK

T0 PIPELINE

PER_EARLY_T0EN

PER_EARLY_C0EN

PAT_PATDATA_x[7:0]

PAT_DATA_VALID

PAT_MASK[3:0]

INPUT_DELAY[7:0]

05557-020

Figure 9. PER_EARLY_T0EN Pipelining

Figure 9 shows the pipelining of PER_EARLY_T0EN (the

period start signal). It is pipelined with MCLK to control the T0

pipelines within the chip. It uses two MCLK pipelines within

the chip to distribute the PER_EARLY_T0EN signal to all of the

T0 pipeline registers.

PER_EARLY_T0EN and PER_EARLY_C0EN, the period start

signals, and the global INPUT_DELAY signals are pipelined

into the ADATE207 with different depths. The PER_EARLY_T0EN

and PER_EARLY_C0EN are pipelined with two MCLK pipelines

prior to the enable pins of the T0 clocked pipelines. The

INPUT_DELAY signals are not pipelined on T0 clock pipelines,

but have only two MCLK pipelines prior to use by the timing

generators.

Figure 10 shows the relative pipelines for INPUT_DELAY and

the period enables.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

ADATE207BBPZ

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