PRELIMINARY
Quad HOTLink II™ Receive
r
CYP15G0401RB
Cypress Semiconductor Corporation 3901 North First Street San Jose
,
CA 95134 408-943-2600
Document #: 38-02111 Rev. ** Revised February 14, 2005
Features
Quad receiver for 195 to 1500 MBaud serial signaling
rate
Aggregate throughput of 6 GBits/second
Second-generation HOTLink
®
technology
Compliant to multiple standards
ESCON, DVB-ASI, Fibre Channel and Gigabit
Ethernet (IEEE802.3z)
8B/10B encoded or 10-bit unencoded data
Selectable parity generate
Selectable output clocking options
MultiFrame™ Receive Framer
Bit and Byte alignment
Comma or full K28.5 detect
Single- or multi-byte framer for byte alignment
Low-latency option
Synchronous LVTTL parallel interface
Optional Elasticity Buffer in Receive Path
Internal Clock/Data Recovery (CDR) PLLs with no
external PLL components
Dual differential PECL-compatible serial inputs per
channel
Internal DC-restoration
Compatible with
Fiber-optic modules
Copper cables
Circuit board traces
JTAG boundary scan
Built-In Self-Test (BIST) for at-speed link testing
Per-channel Link Quality Indicator
Analog signal detect
Digital signal detect
Low power 2.1W @ 3.3V typical
Single 3.3V supply
256-ball thermally enhanced BGA
Pb free package available
0.25µ BiCMOS technology
Functional Description
The CYP15G0401RB Quad HOTLink II™ Receiver is a
point-to-point or point-to-multipoint communications building
block allowing the transfer of data over high-speed serial links
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 195-to-1500 MBaud
per serial link.
Each receive channel accepts serial data and converts it to
parallel data, decodes the data into characters, and presents
these characters to an Output Register. Figure 1 illustrates
typical connections between independent host systems and
corresponding CYP15G0401TB and CYP15G0401RB parts.
Figure 1. HOTLink II System Connections
System Host
Serial Link
10
10
10
10
System Host
10
10
10
Serial Link
Serial Link
Serial Link
Backplane or
Cabled
Connections
CYP15G0401RB
CYP15G0401TB
10
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PRELIMINARY
CYP15G0401RB
Document #: 38-02111 Rev. ** Page 2 of 35
As a second-generation HOTLink device, the
CYP15G0401RB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data, command, and BIST) with other
HOTLink devices. The receivers (RX) of the CYP15G0401RB
Quad HOTLink II consist of four byte-wide channels. Each
channel accepts a serial bit-stream from one of two
PECL-compatible differential line receivers and, using a
completely integrated PLL Clock Synchronizer, recovers the
timing information necessary for data reconstruction. Each
recovered serial stream is deserialized and framed into
characters, 8B/10B decoded, and checked for transmission
errors. Recovered decoded characters are then written to an
internal Elasticity Buffer, and presented to the destination host
system. The integrated 8B/10B Decoder may be bypassed for
systems that present externally encoded or scrambled data at
the parallel interface.
The parallel I/O interface may be configured for numerous
forms of clocking to provide the highest flexibility in system
architecture. The receive interface may be configured to
present data relative to a recovered clock or to a local training
clock.
Each receive channel contains an independent BIST pattern
checker. This BIST hardware allows at-speed testing of the
high-speed serial data paths in each receive section, and
across the interconnecting links.
HOTLink II devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed,
point-to-point serial links. Some applications include
interconnecting backplanes on switches, routers, servers and
video transmission systems.
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PRELIMINARY
CYP15G0401RB
Document #: 38-02111 Rev. ** Page 3 of 35
CYP15G0401RB Receiver Logic Block Diagram
Decoder
8B/10B
Framer
Deserializer
RX
Decoder
8B/10B
Framer
Deserializer
RX
Decoder
8B/10B
Framer
Deserializer
RX
Decoder
8B/10B
Framer
Deserializer
RX
RXDA[7:0]
RXDB[7:0]
RXDC[7:0]
RXDD[7:0]
INA1
±
INA2
±
INB1
±
INB2
±
INC1
±
INC2
±
IND1
±
IND2
±
Elasticity
Buffer
Elasticity
Buffer
Elasticity
Buffer
Elasticity
Buffer
RXSTA[2:0]
RXSTB[2:0]
RXSTC[2:0]
RXSTD[2:0]
x11
x11
x11
x11
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CYP15G0401RB-BGXC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC RECEIVER HOTLINK 256LBGA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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