CYP15G0401RB-BGXC Datasheet CYP15G0401RB-BGC, CYP15G0401RB-BGI, CYP15G0401RB-BGXC | P7-P9

PRELIMINARY

CYP15G0401RB

Document #: 38-02111 Rev. ** Page 7 of 35

Pin Descriptions

CYP15G0401RB Quad HOTLink II Receiver

Pin Name I/O Characteristics Signal Description

Receive Path Data Signals

RXDA[7:0]

RXDB[7:0]

RXDC[7:0]

RXDD[7:0]

LVTTL Output,

synchronous to the

selected RXCLKx

↑

output

(or TRGCLK

↑

input

[2]

when RXCKSEL = LOW)

Parallel Data Output

. These outputs change following the rising edge of the selected

receive interface clock.

When the Decoder is enabled (DECMODE = HIGH or MID), these outputs represent

either received data or special characters. The status of the received data is represented

by the values of RXSTx[2:0].

When the Decoder is bypassed (DECMODE = LOW), RXDx[7:0] become the higher order

bits of the 10-bit received character. See

Table 7

for details.

RXSTA[2:

RXSTB[2:

RXSTC[2:

RXSTD[2:

LVTTL Output,

synchronous to the

selected RXCLKx

↑

output

(or TRGCLK

↑

input

[2]

when RXCKSEL = LOW)

Parallel Status Output

. These outputs change following the rising edge of the selected

receive interface clock.

When the Decoder is bypassed (DECMODE = LOW), RXSTx[1:0] become the two

low-order bits of the 10-bit received character, while RXSTx[2] = HIGH indicates the

presence of a Comma character in the Output Register. See

Table 7

for details.

When the Decoder is enabled (DECMODE = HIGH or MID), RXSTx[2:0] provide status

of the received signal. See

Table 9

and

Table 10

for a list of Receive Character status.

RXOPA

RXOPB

RXOPC

RXOPD

Three-state, LVTTL

Output, synchronous to

the selected

RXCLKx

↑

output

(or TRGCLK

↑

input

[2]

when RXCKSEL = LOW)

Receive Path Odd Parity

. When parity generation is enabled (PARCTL

≠

LOW), the

parity output at these pins is valid for the data on the associated RXDx bus bits. When

parity generation is disabled (PARCTL = LOW) these output drivers are disabled (High-Z).

Receive Path Clock and Clock Control

RXRATE LVTTL Input, static control

input, internal pull-down

Receive Clock Rate Select

. When LOW, the RXCLKx

recovered clock outputs are

complementary clocks operating at the recovered character rate. Data for the associated

receive channels should be latched on the rising edge of RXCLKx+ or falling edge of

RXCLKx–.

When HIGH, the RXCLKx± recovered clock outputs are complementary clocks operating

at half the character rate. Data for the associated receive channels should be latched

alternately on the rising edge of RXCLKx+ and RXCLKx–.

When TRGCLK± is selected to clock the output registers (RXCKSELx = LOW), RXRATEx

is not interpreted. The RXCLKA± and RXCLKC± output clocks will follow the frequency

and duty cycle of TRGCLK±.

TRGRATE LVTTL Input,

static control input,

internal pull-down

Training Clock Rate Select

. When TRGCLK is selected to clock the receive parallel

interfaces (RXCKSEL = LOW), the TRGRATE input also determines if the clocks on the

RXCLKA

and RXCLKC

outputs are full or half-rate. When TRGRATE = HIGH

(TRGCLK is half-rate) and RXCKSEL = LOW, the RXCLKA± and RXCLKC± output clocks

are also half-rate clocks and follow the frequency and duty cycle of the TRGCLK input.

When TRGRATE = LOW (TRGCLK is full-rate) and RXCKSEL = LOW, the RXCLKA± and

RXCLKC± output clocks are full-rate clocks and follow the frequency and duty cycle of

the TRGCLK input.

FRAMCH

Three-level Select

[3]

static control input

Framing Character Select

. Used to select the character or portion of a character used

for character framing of the received data streams. When MID, the Framer looks for both

positive and negative disparity versions of the eight-bit Comma character. When HIGH,

the Framer looks for both positive and negative disparity versions of the K28.5 character.

Configuring FRAMCHAR to LOW is reserved for component test.

RFEN LVTTL Input,

asynchronous,

internal pull-down

Reframe Enable for All Channels

. Active HIGH. When HIGH, the framers in all four

channels are enabled to frame per the presently enabled framing mode as selected by

RFMODE and selected framing character as selected by FRAMCHAR.

Notes:

2. When TRGCLK is configured for half-rate operation (TRGRATE = HIGH), these inputs are sampled (or the outputs change) relative to both the rising and falling

edges of TRGCLK.

3. Three-level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and

HIGH. The LOW level is usually implemented by direct connection to V

(ground). The HIGH level is usually implemented by direct connection to V

. When

not connected or allowed to float, a Three-level select input will self-bias to the MID level.

[+] Feedback

PRELIMINARY

CYP15G0401RB

Document #: 38-02111 Rev. ** Page 8 of 35

RXCLKA

RXCLKB

RXCLKC

RXCLKD

Three-state, LVTTL

Output clock or static

control input

Receive Character Clock Output or Clock Select Input

. When configured such that all

output data paths are clocked by the recovered clock (RXCKSEL = MID), these true and

complement clocks are the receive interface clocks which are used to control timing of

output data (RXDx[7:0], RXSTx[2:0] and RXOPx). These clocks are output continuously

at either the dual-character rate (1/20

the serial bit-rate) or character rate (1/10

the

serial bit-rate) of the data being received, as selected by RXRATE.

When configured such that all output data paths are clocked by TRGCLK instead of a

recovered clock (RXCKSEL = LOW), the RXCLKA

and RXCLKC

output drivers present

a buffered and delayed form of TRGCLK. RXCLKA

and RXCLKC

are buffered forms

of TRGCLK that are slightly different in phase. This phase difference allows the user to

select the optimal setup/hold timing for their specific interface.

RXCKSEL Three-level Select

[3]

static control input

Receive Clock Mode

. Selects the receive clock source used to transfer data to the

Output Registers.

When LOW, all four Output Registers are clocked by TRGCLK. RXCLKB

and RXCLKD

outputs are disabled (High-Z), and RXCLKA

and RXCLKC

present buffered and

delayed forms of TRGCLK.

When MID, each RXCLKx

output follows the recovered clock for the respective channel,

as selected by RXRATE. When the 10B/8B Decoder and Elasticity Buffer are bypassed

(DECMODE = LOW), RXCKSEL must be MID.

When HIGH and the receive channels are operated in independent mode (RX modes 0

and 2), RXCLKA

and RXCLKC

output the recovered clock from receive channel A, B,

C, or D, as selected by RXCLKB+ and RXCLKD+. This output clock may operate at the

character-rate or half the character-rate as selected by RXRATE.

DECMOD

Three-level Select

[3]

static control input

Decoder Mode Select

. This input selects the behavior of the Decoder block. When LOW,

the Decoder is bypassed and raw 10-bit characters are passed to the Output Register.

When the Decoder is bypassed, RXCKSEL must be MID.

When MID, the Decoder is enabled and the Cypress decoder table for Special Code

characters is used.

When HIGH, the Decoder is enabled and the alternate decoder table for Special Code

characters is used. See

Table 15

for a list of the Special Codes supported in both encoded

modes.

RFMODE Three-level Select

[3]

static control input

Reframe Mode Select

. Used to select the type of character framing used to adjust the

character boundaries (based on detection of one or more framing characters in the

received serial bit stream). This signal operates with the type of framing character

selected.

When LOW, the Low-Latency Framer is selected. This will frame on each occurrence of

the selected framing character(s) in the received data stream. This mode of framing

stretches the recovered character-rate clock for one or multiple cycles to align that clock

with the recovered data.

When MID, the Cypress-mode Multi-Byte parallel Framer is selected. This requires a pair

of the selected framing character(s), on identical 10-bit boundaries, within a span of 50

bits, before the character boundaries are adjusted. The recovered character clock

remains in the same phase regardless of character offset.

When HIGH, the alternate mode Multi-Byte parallel Framer is selected. This requires

detection of the selected framing character(s) of the allowed disparities in the received

serial bit stream, on identical 10-bit boundaries, on four directly adjacent characters. The

recovered character clock remains in the same phase regardless of character offset.

Pin Descriptions

(continued)

CYP15G0401RB Quad HOTLink II Receiver

Pin Name I/O Characteristics Signal Description

[+] Feedback

PRELIMINARY

CYP15G0401RB

Document #: 38-02111 Rev. ** Page 9 of 35

Device Control Signals

PARCTL Three-level Select

[3]

static control input

Parity Generate Control

. Used to control the different parity generate functions. When

LOW, parity checking is disabled, and the RXOPx outputs are all disabled (High-Z). When

MID, and the 10B/8B Decoder is enabled (DECMODE

≠

LOW), ODD parity is generated

for the RXDx[7:0] outputs and presented on RXOPx. When the Decoder is disabled

(DECMODE

LOW), ODD parity is generated for the RXDx[7:0] and RXSTx[1:0] outputs

and presented on RXOPx. When HIGH, parity generation is enabled. ODD parity is

generated for the RXDx[7:0] and RXSTx[2:0] outputs and presented on RXOPx. See

Table 8

for details.

SPDSEL Three-level Select

[3]

static control input

Serial Rate Select

. This input specifies the operating bit-rate range of the receive PLLs.

LOW = 195–400 MBd, MID = 400–800 MBd, HIGH = 800–1500 MBd. When SPDSEL is

LOW, setting TRGRATE = HIGH (Half-rate Training Clock) is invalid.

TRSTZ LVTTL Input,

internal pull-up

Device Reset

. Active LOW. Initializes all state machines and counters in the device.

When sampled LOW by the rising edge of TRGCLK

↑

, this input resets the internal state

machines and sets the Elasticity Buffer pointers to a nominal offset. When the reset is

removed (TRSTZ sampled HIGH by TRGCLK

↑

), the status and data outputs will become

deterministic in less than 16 TRGCLK cycles. The BISTLE and RXLE latches are reset

by TRSTZ. If the Elasticity Buffer is used, TRSTZ should be applied after power up to

initialize the internal pointers into these memory arrays.

TRGCLK

Differential LVPECL or

single-ended

LVTTL Input Clock

Training Clock

. This clock is used as the centering frequency of the Range Controller

block of the Receive CDR PLLs, via the Clock Multiplier. This input clock may also be

selected to clock the receive parallel interfaces. When driven by a single-ended LVCMOS

or LVTTL clock source, connect the clock source to either the true or complement

TRGCLK input, and leave the alternate TRGCLK input open (floating). When driven by

an LVPECL clock source, the clock must be a differential clock, using both inputs. When

RXCKSEL = LOW, the Elasticity Buffer is enabled and TRGCLK is used as the clock for

the parallel receive data (output) interface.

If the Elasticity Buffer is used, framing characters will be inserted or deleted to/from the

data stream to compensate for frequency differences between the training clock and

recovered clock. When an addition happens, a K28.5 will be appended immediately after

a framing character is detected in the Elasticity Buffer. When deletion happens, a framing

character will be removed from the data stream when detected in the Elasticity Buffer.

Analog I/O and Control

INA1

INB1

INC1

IND1

LVPECL Differential Input

Primary Differential Serial Data Inputs

. These inputs accept the serial data stream for

deserialization and decoding. The INx1

serial streams are passed to the receiver Clock

and Data Recovery (CDR) circuits to extract the data content when INSELx = HIGH.

INA2

INB2

INC2

IND2

LVPECL Differential Input

Secondary Differential Serial Data Inputs

. These inputs accept the serial data stream

for deserialization and decoding. The INx2

serial streams are passed to the receiver

Clock and Data Recovery (CDR) circuits to extract the data content when INSELx = LOW.

INSELA

INSELB

INSELC

INSELD

LVTTL Input,

asynchronous

Receive Input Selector

. Determines which external serial bit stream is passed to the

receiver Clock and Data Recovery circuit. When HIGH, the INx1

input is selected. When

LOW, the INx2

input is selected.

SDASEL Three-level Select

[3]

static configuration input

Signal Detect Amplitude Level Select

. Allows selection of one of three predefined

amplitude trip points for a valid signal indication, as listed in

Table 1

BISTLE LVTTL Input,

asynchronous,

internal pull-up

Receive BIST Latch Enable

. Active HIGH. When BISTLE = HIGH, the signals on the

BRE[3:0] inputs directly control the receive BIST enables. When the BRE[x] input is LOW,

the associated receive channel is configured to compare the BIST sequence. When the

BRE[x] input is HIGH, the associated receive channel is configured for normal data

reception. The specific mapping of BRE[3:0] signals to receive BIST enables is listed in

Table 2

. When BISTLE returns LOW, the last values present on BRE[3:0] are captured

in the internal BIST Enable Latch. When the latch is closed, if the device is reset (TRSTZ

is sampled LOW), the latch is reset to disable BIST on all receive channels.

Pin Descriptions

(continued)

CYP15G0401RB Quad HOTLink II Receiver

Pin Name I/O Characteristics Signal Description

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CYP15G0401RB-BGXC

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Manufacturer:

Cypress Semiconductor

Description:

IC RECEIVER HOTLINK 256LBGA

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