CYP15G0401RB-BGXC Datasheet CYP15G0401RB-BGC, CYP15G0401RB-BGI, CYP15G0401RB-BGXC | P13-P15

PRELIMINARY

CYP15G0401RB

Document #: 38-02111 Rev. ** Page 13 of 35

character. To reduce the impact on external circuits that make

use of a recovered clock, the clock period is not stretched by

more than two bit-periods in any one clock cycle. When

operated with a character-rate output clock (RXRATE = LOW),

the output of properly framed characters may be delayed by

up to nine character-clock cycles from the detection of the

selected framing character. When operated with a

half-character-rate output clock (RXRATE = HIGH), the output

of properly framed characters may be delayed by up to

fourteen character-clock cycles from the detection of the

selected framing character.

When RFMODE = MID (open), the Cypress-mode Multi-Byte

Framer is selected. The required detection of multiple framing

characters makes the associated link much more robust to

incorrect framing due to aliased framing characters in the data

stream. In this mode, the Framer does not adjust the character

clock boundary, but instead aligns the character to the already

recovered character clock. This ensures that the recovered

clock does not contain any significant phase changes or hops

during normal operation or framing, and allows the recovered

clock to be replicated and distributed to other external circuits

or components using PLL-based clock distribution elements.

In this framing mode, the character boundaries are only

adjusted if the selected framing character is detected at least

twice within a span of 50 bits, with both instances on identical

10-bit character boundaries.

When RFMODE = HIGH, the Alternate-mode Multi-Byte

Framer is enabled. Like the Cypress-mode Multi-Byte Framer,

multiple framing characters must be detected before the

character boundary is adjusted. In this mode, the Framer does

not adjust the character clock boundary, but instead aligns the

character to the already recovered character clock. In this

mode, the data stream must contain a minimum of four of the

selected framing characters, received as consecutive

characters, on identical 10-bit boundaries, before character

framing is adjusted.

Framing for all channels is enabled when RFEN = HIGH. If

RFEN = LOW, the Framer for each channel is disabled. When

the framers are disabled, no changes are made to the

recovered character boundaries on any channel, regardless of

the presence of framing characters in the data stream.

10B/8B Decoder Block

The Decoder logic block performs three primary functions:

• decoding the received transmission characters back into

Data and Special Character codes

• comparing generated BIST patterns with received

characters to permit at-speed link and device testing

• generation of ODD parity on the decoded characters.

10B/8B Decoder

The framed parallel output of each Deserializer Shifter is

passed to the 10B/8B Decoder where, if the Decoder is

enabled (DECMODE

≠

LOW), it is transformed from a 10-bit

transmission character back to the original Data and Special

Character codes. This block uses the 10B/8B Decoder

patterns in

Table 14

and

Table 15

of this data sheet. Valid data

characters are indicated by a 000b bit-combination on the

associated RXSTx[2:0] status bits, and Special Character

codes are indicated by a 001b bit-combination on these same

status outputs. Framing characters, invalid patterns, disparity

errors, and synchronization status are presented as alternate

combinations of these status bits.

The 10B/8B Decoder operates in two normal modes, and can

also be bypassed. The operating mode for the Decoder is

controlled by the DECMODE input.

When DECMODE = LOW, the Decoder is bypassed and raw

10-bit characters are passed to the Output Register. In this

mode the Receive Elasticity Buffers are bypassed, and

RXCKSEL must be MID. This clock mode generates separate

RXCLKx

outputs for each receive channel.

When DECMODE = MID (or open), the 10-bit transmission

characters are decoded using

Table 14

and

Table 15

Received Special Code characters are decoded using the

Cypress column of

Table 15

When DECMODE = HIGH, the 10-bit transmission characters

are decoded using

Table 14

and

Table 15

. Received Special

Code characters are decoded using the Alternate column of

Table 15

Receive BIST Operation

The Receiver interfaces contain internal pattern generators

that can be used to validate both device and link operation.

These generators are enabled by the associated BRE[x]

signals listed in

Table 2

(when the BISTLE latch enable input

is HIGH). When enabled, a register in the associated receive

channel becomes a pattern generator and checker by logically

converting to a Linear Feedback Shift Register (LFSR). This

LFSR generates a 511-character sequence that includes all

Data and Special Character codes, including the explicit

violation symbols. This provides a predictable yet pseudo-

random sequence that can be matched to an identical LFSR

in the attached Transmitter(s), the CYP15G0401TB for

example. If the receive channels are configured for common

clock operation (RXCKSEL

≠

MID) each pass must be

preceded by a 16-character Word Sync Sequence. Please

note that BIST cannot be used in a common clock configu-

ration (RXCKSEL

≠

MID) when using the CYP15G0401TB

device as the BIST generator, as the 16-character Word Sync

Sequence will not be present in the BIST pattern. When

synchronized with the received data stream, the associated

Receiver checks each character in the Decoder with each

character generated by the LFSR and indicates compare

errors and BIST status at the RXSTx[2:0] bits of the Output

Table 10

for details.

When the BISTLE signal is HIGH, any BRE[x] input that is

LOW enables the BIST generator/checker in the associated

Receive channel. When BISTLE returns LOW, the values of

all BRE[x] signals are captured in the BIST Enable Latch.

These values remain in the BIST Enable Latch until BISTLE is

returned HIGH. All captured signals in the BIST Enable Latch

are set HIGH (i.e., BIST is disabled) following a device reset

(TRSTZ

is sampled LOW).

When BIST is first recognized as being enabled in the

Receiver, the LFSR is preset to the BIST-loop start-code of

D0.0. This D0.0 character is sent only once per BIST loop. The

status of the BIST progress and any character mismatches is

presented on the RXSTx[2:0] status outputs.

Code rule violations or running disparity errors that occur as

part of the BIST loop do not cause an error indication.

RXSTx[2:0] indicates 010b or 100b for one character period

per BIST loop to indicate loop completion. This status can be

used to check test pattern progress. These same status values

[+] Feedback

PRELIMINARY

CYP15G0401RB

Document #: 38-02111 Rev. ** Page 14 of 35

are presented when the Decoder is bypassed and BIST is

enabled on a receive channel.

The status reported on RXSTx[2:0] by the BIST state machine

are listed in

Table 10

. When Receive BIST is enabled, the

same status is reported on the receive status outputs

regardless of the state of DECMODE.

The specific patterns checked by each receiver are described

in detail in the Cypress application note “HOTLink Built-In

Self-Test.” The sequence compared by the CYP15G0401RB

when RXCKSEL = MID is identical to that in the CY7B933 and

CY7C924DX, allowing interoperable systems to be built when

used at compatible serial signaling rates.

If the number of invalid characters received ever exceeds the

number of valid characters by sixteen, the receive BIST state

machine aborts the compare operations and resets the LFSR

to the D0.0 state to look for the start of the BIST sequence

again.

When the receive paths are configured for common clock

operation (RXCKSEL

≠

MID), each pass must be preceded by

a 16-character Word Sync Sequence to allow output buffer

alignment and management of clock frequency variations (see

CYP15G0401TB datasheet for details on how to send a

16-character Word Sync Sequence from the remote trans-

mitter).

The BIST state machine requires the characters to be correctly

framed for it to detect the BIST sequence. If the Low Latency

Framer is enabled (RFMODE = LOW), the Framer will

misalign to an aliased framing character within the BIST

sequence. If the Alternate Multi-Byte Framer is enabled

(RFMODE = HIGH) and the Receiver outputs are clocked

relative to a recovered clock, it is necessary to frame the

Receiver before BIST is enabled.

Receive Elasticity Buffer

Each receive channel contains an Elasticity Buffer that is

designed to support multiple clocking modes. These buffers

allow data to be read using an Elasticity Buffer read-clock that

is asynchronous in both frequency and phase from the

Elasticity Buffer write clock, or to use a read clock that is

frequency coherent but with uncontrolled phase relative to the

Elasticity Buffer write clock.

Each Elasticity Buffer is 10-characters deep, and supports a

twelve-bit wide data path. It is capable of supporting a decoded

character, three status bits, and a parity bit for each character

present in the buffer. The write clock for these buffers is always

the recovered clock for the associated read channel.

The read clock for the Elasticity Buffers may come from one of

three selectable sources. It may be a

• character-rate TRGCLK (RXCKSEL = LOW and

DECMODE

≠

LOW)

• recovered clock from an alternate receive channel

(RXCKSEL = HIGH and DECMODE

≠

LOW).

The Elasticity Buffers are bypassed whenever the Decoders

are bypassed (DECMODE = LOW). When the Decoders and

Elasticity Buffers are bypassed, RXCKSELx must be set to

MID.

Receive Normal Data Operation

When RXCKSEL = LOW, all four receive channels are clocked

by TRGCLK. RXCLKB

and RXCLKD

outputs are disabled

(High-Z), and the RXCLKA

and RXCLKC

outputs present a

buffered and delayed form of TRGCLK. In this mode, the

Receive Elasticity Buffers are enabled. For TRGCLK clocking,

the Elasticity Buffers must be able to insert K28.5 characters

and delete framing characters as appropriate.

The insertion of a K28.5 or deletion of a framing character can

occur at any time on any channel, however, the actual timing

on these insertions and deletions is controlled in part by the

how the attached remote transmitter sends its data. Insertion

of a K28.5 character can only occur when the receiver has a

framing character in the Elasticity Buffer. Likewise, to delete a

framing character, one must also be present in the Elasticity

Buffer. To prevent a receive buffer overflow or underflow on a

receive channel, a minimum density of framing characters

must be present in the received data streams.

When RXCKSEL = MID (or open), each received channel

Output Register is clocked by the recovered clock for that

channel. Since no characters may be added or deleted, the

receiver Elasticity Buffer is bypassed.

When RXCKSEL = HIGH in independent channel mode, all

channels are clocked by the selected recovered clock. This

selection is made using the RXCLKB+ and RXCLKD+ signals

as inputs per

Table 5

. This selected clock is always output on

RXCLKA

and RXCLKC

. In this mode the Receive Elasticity

Buffers are enabled. When data is output using a recovered

clock (RXCKSEL = HIGH), the receive channels are not

allowed to insert and delete characters, except as necessary

for Elasticity Buffer alignment.

When the Elasticity Buffer is used, prior to reception of valid

data, a Word Sync Sequence (or at least four framing

characters) must be received to center the Elasticity Buffers.

The Elasticity Buffer may also be centered by a device reset

operation initiated by TRSTZ

input. However, following such

an event, the CYP15G0401RB also requires a framing event

before it will correctly decode characters. When RXCKSEL =

HIGH, since the Elasticity Buffer is not allowed to insert or

delete framing characters, the transmit clocks on all received

channels must all be from a common source.

Power Control

The CYP15G0401RB supports user control of the powered up

or down state of each receive channel. The receive channels

are controlled by the RXLE signal and the values present on

the BRE[3:0] bus. Powering down unused channels will save

power and reduce system heat generation. Controlling system

power dissipation will improve the system performance.

Receive Channels

When RXLE is HIGH, the signals on the BRE[3:0] inputs

directly control the power enables for the receive PLLs and

analog circuits. When a BRE[3:0] input is HIGH, the

associated receive channel [A through D] PLL and analog

logic are active. When a BRE[3:0] input is LOW, the

Table 5. Independent Recovered Clock Select

RXCLKB+ RXCLKD+

RXCLKA±/RXCLKC± Clock

Source

0 0 RXCLKA

0 1 RXCLKB

1 0 RXCLKC

1 1 RXCLKD

[+] Feedback

PRELIMINARY

CYP15G0401RB

Document #: 38-02111 Rev. ** Page 15 of 35

associated receive channel [A through D] PLL and analog

circuits are powered down. When RXLE returns LOW, the last

values present on the BRE[3:0] inputs are captured in the

Receive Channel Enable Latch. The specific BRE[3:0] input

signal associated with a receive channel is listed in

Table 2

Any disabled receive channel will indicate a constant LFIx

output. When a disabled receive channel is re-enabled, the

status of the associated LFIx

output and data on the parallel

outputs for the associated channel may be indeterminate for

up to 2 ms.

Device Reset State

When the CYP15G0401RB is reset by assertion of TRSTZ,

the Receive Enable Latches are both cleared, and the BIST

Enable Latch is preset. In this state, all receive channels are

disabled, and BIST is disabled on all channels.

Following a device reset, it is necessary to enable the receive

channels used for normal operation. This can be done by

sequencing the appropriate values on the BRE[3:0] inputs

while the RXLE signals are raised and lowered. For systems

that do not require dynamic control of power, or want the

device to power up in a fixed configuration, it is also possible

to strap the RXLE control signal HIGH to permanently enable

its associated latches. Connection of the associated BRE[3:0]

signals to a stable HIGH will then enable the respective

receive channels as soon as the TRSTZ

signal is deasserted.

Output Bus

Each receive channel presents a 12-signal output bus

consisting of

• an eight-bit data bus

• a three-bit status bus

• a parity bit.

The bit assignments of the Data and Status are dependent on

the setting of DECMODE. The bits are assigned as per

Table 6

When the 10B/8B Decoder is bypassed (DECMODE = LOW),

the framed 10-bit character and a single status bit (COMDET)

are presented at the receiver Output Register. The status

output indicates if the character in the Output Register is one

of the selected framing characters. The bit usage and mapping

of the external signals to the raw 10B transmission character

is shown in

Table 7

The COMDETx outputs are HIGH when the character in the

Output Register for the associated channel contains the

selected framing character at the proper character boundary,

and LOW for all other bit combinations.

When the Low-Latency Framer and half-rate receive port

clocking are also enabled (RFMODE = LOW, RXRATE =

HIGH, and RXCKSEL

≠

LOW), the Framer will stretch the

recovered clock to the nearest 20-bit boundary such that the

rising edge of RXCLKx+ occurs when COMDETx is present on

the associated output bus.

Notes:

9. The RXOPx outputs are also driven from the associated Output Register, but their interpretation is under the separate control of PARCTL.

Table 6. Output Register Bit Assignments

[9]

Signal Name DECMODE = LOW

DECMODE = MID or

HIGH

RXSTx[2]

(LSB)

COMDETx RXSTx[2]

RXSTx[1] DOUTx[0] RXSTx[1]

RXSTx[0] DOUTx[1] RXSTx[0]

RXDx[0] DOUTx[2] RXDx[0]

RXDx[1] DOUTx[3] RXDx[1]

RXDx[2] DOUTx[4] RXDx[2]

RXDx[3] DOUTx[5] RXDx[3]

RXDx[4] DOUTx[6] RXDx[4]

RXDx[5] DOUTx[7] RXDx[5]

RXDx[6] DOUTx[8] RXDx[6]

RXDx[7]

(MSB)

DOUTx[9] RXDx[7]

[+] Feedback

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CYP15G0401RB-BGXC

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Cypress Semiconductor

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IC RECEIVER HOTLINK 256LBGA

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