PRELIMINARY
CYP15G0401RB
Document #: 38-02111 Rev. ** Page 19 of 35
Receive BIST
Detected LOW
Monitor Data
Received
RXSTx =
BIST_START (101)
No
RX PLL
Out of Lock
Yes, RXSTx = BIST_COMMAND_COMPARE (001)
OR BIST_DATA_COMPARE (000)
Compare
Next Character
Auto-Abort
Condition
Mismatch
End-of-BIST
State
Yes, RXSTx =
BIST_LAST_BAD (100)
Yes
No
No, RXSTx =
BIST_ERROR (110)
Data or
Command
Match
Command
RXSTx =
BIST_COMMAND_COMPARE (001)
End-of-BIST
State
Data
Yes, RXSTx =
BIST_LAST_GOOD (010)
No
RXSTx =
BIST_DATA_COMPARE (000)
Figure 2. Receive BIST State Machine
Elasticity
Buffer Error
Start of
BIST Detected
RXSTx =
BIST_WAIT (111)
Yes
RXSTx =
BIST_START (101)
No
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PRELIMINARY
CYP15G0401RB
Document #: 38-02111 Rev. ** Page 20 of 35
Maximum Ratings
(Above which the useful life may be impaired. User guidelines
only, not tested.)
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with Power Applied....–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +3.8V
DC Voltage Applied to LVTTL Outputs
in High-Z State .......................................–0.5V to V
CC
+ 0.5V
Output Current into LVTTL Outputs (LOW)..................60 mA
DC Input Voltage....................................–0.5V to V
CC
+ 0.5V
Static Discharge Voltage...........................................> 2000V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Power-up Requirements
The CYP15G0401RB requires one power-supply. The voltage
on any input or I/O pin cannot exceed the power pin during
power-up
Operating Range
Range Ambient Temperature V
CC
Commercial 0°C to +70°C +3.3V
±
5%
Industrial –40°C to +85°C +3.3V
±
5%
CYP15G0401RB DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
LVTTL-compatible Outputs
V
OHT
Output HIGH Voltage I
OH
=
4 mA, V
CC
= Min. 2.4 V
CC
V
V
OLT
Output LOW Voltage I
OL
= 4 mA, V
CC
= Min. 0 0.4 V
I
OST
Output Short Circuit Current V
OUT
= 0V
[12]
–20 –100 mA
I
OZL
High-Z Output Leakage Current –20 20
µ
A
LVTTL-compatible Inputs
V
IHT
Input HIGH Voltage 2.0 V
CC
+ 0.3 V
V
ILT
Input LOW Voltage –0.5 0.8 V
I
IHT
Input HIGH Current TRGCLK Input, V
IN
= V
CC
1.5 mA
Other Inputs, V
IN
= V
CC
+40
µ
A
I
ILT
Input LOW Current TRGCLK Input, V
IN
= 0.0V 1.5 mA
Other Inputs, V
IN
= 0.0V 40
µ
A
I
IHPDT
Input HIGH Current with internal pull-down V
IN
= V
CC
+200
µ
A
I
ILPUT
Input LOW Current with internal pull-up V
IN
= 0.0V –200
µ
A
LVDIFF Inputs: TRGCLK±
V
DIFF
[13]
Input Differential Voltage 400 V
CC
mV
V
IHHP
Highest Input HIGH Voltage 1.2 V
CC
V
V
ILLP
Lowest Input LOW voltage 0.0 V
CC/2
V
V
COMREF
[14]
Common Mode Range 1.0 V
CC
– 1.2V V
Three-level Inputs
V
IHH
Three-level Input HIGH Voltage Min.
V
CC
Max. 0.87 * V
CC
V
CC
V
V
IMM
Three-level Input MID Voltage Min.
V
CC
Max. 0.47 * V
CC
0.53 * V
CC
V
V
ILL
Three-level Input LOW Voltage Min.
V
CC
Max. 0.0 0.13 * V
CC
V
I
IHH
Input HIGH Current V
IN
= V
CC
200
µ
A
I
IMM
Input MID current V
IN
= V
CC
/2 –50 50
µ
A
I
ILL
Input LOW current V
IN
= GND –200
µ
A
Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±, INC1±, INC2±, IND1±, IND2±
V
DIFFS
[13]
Input Differential Voltage |(IN+)
(IN
)| 100 1200 mV
V
IHE
Highest Input HIGH Voltage V
CC
V
Notes:
12.Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
13.This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the
true (+) input is more positive than the complement () input. A logic-0 exists when the complement () input is more positive than true (+) input.
14.The common mode range defines the allowable range of TRGCLK+ and TRGCLKwhen TRGCLK+ = TRGCLK. This marks the zero-crossing between the
true and complement inputs as the signal switches between a logic-1 and a logic-0.
[+] Feedback
PRELIMINARY
CYP15G0401RB
Document #: 38-02111 Rev. ** Page 21 of 35
Test Loads and Waveforms
V
ILE
Lowest Input LOW Voltage V
CC
– 2.0 V
I
IHE
Input HIGH Current V
IN
= V
IHE
Max. 1350
µ
A
I
ILE
Input LOW Current V
IN
= V
ILE
Min. 700
µ
A
V
COM
[15, 16]
Common Mode Input Range V
CC
– 1.95 V
CC
– 0.05 V
Power Supply
Parameter Description Test Conditions Typ.
[17]
Max.
[18]
Unit
I
CC
Power Supply Current
TRGCLK
= Max.
Commercial 660 690 mA
Industrial 740 mA
I
CC
Power Supply Current
TRGCLK
= 125 MHz
Commercial 640 650 mA
Industrial 700 mA
CYP15G0401RB DC Electrical Characteristics
Over the Operating Range
(continued)
Parameter Description Test Conditions Min. Max. Unit
2.0V
0.8V
GND
2.0V
0.8V
80%
20%
80%
20%
3.0V
V
th
= 1.4V
270 ps
270 ps
[20]
V
th
= 1.4V
3.3V
R1
R2
R1 = 590
R2 = 435
(Includes fixture and
probe capacitance)
C
L
7 pF
(a) LVTTL Output Test Load
C
L
(b) LVTTL Input Test Waveform
(c) CML/LVPECL Input Test Waveform
1 ns
1 ns
V
IHE
V
ILE
V
IHE
V
ILE
[19]
CYP15G0401RB AC Characteristics
Over the Operating Range
Parameter Description Min. Max. Unit
CYP15G0401RB Receiver LVTTL Switching Characteristics
Over the Operating Range
f
RS
RXCLKx Clock Output Frequency 9.75 150 MHz
t
RXCLKP
RXCLKx Period 6.66 102.56 ns
t
RXCLKH
RXCLKx HIGH Time (RXRATE = LOW) 2.33
[21]
26.64 ns
RXCLKx HIGH Time (RXRATE = HIGH) 5.66 52.28 ns
t
RXCLKL
RXCLKx LOW Time (RXRATE = LOW) 2.33
[21]
26.64 ns
RXCLKx LOW Time (RXRATE = HIGH) 5.66 52.28 ns
t
RXCLKD
RXCLKx Duty Cycle centered at 50% –1.0 +1.0 ns
t
RXCLKR
[21]
RXCLKx Rise Time 0.3 1.2 ns
t
RXCLKF
[21]
RXCLKx Fall Time 0.3 1.2 ns
Notes:
15.The common mode range defines the allowable range of INPUT+ and INPUTwhen INPUT+ = INPUT. This marks the zero-crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
16.Not applicable for AC-coupled interfaces. For AC-coupled interfaces, V
DIFFS
requirement still needs to be satisfied.
17.Maximum I
CC
is measured with V
CC
= MAX, RXCKSEL = LOW, with all TX and RX channels and Serial Line Drivers enabled, sending a continuous alternating
01 pattern to the associated receive channel, and outputs unloaded.
18.Typical I
CC
is measured under similar conditions except with V
CC
= 3.3V, T
A
= 25°C, RXCKSEL = LOW, with all RX channels enabled receiving a continuous
alternating 01 pattern to the associated receive channel. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.
19.Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only. 5-pF differential load reflects tester capacitance,
and is recommended at low data rates only.
20.The LVTTL switching threshold is 1.4V. All timing references are made relative to the point where the signal edges crosses the threshold voltage.
21.Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
[+] Feedback

CYP15G0401RB-BGXC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC RECEIVER HOTLINK 256LBGA
Lifecycle:
New from this manufacturer.
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