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CYP15G0401RB-BGXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
PRELIMINARY
CYP15G0401RB
Document #: 38-02111 Rev. ** Page 4 of 35
INA1+
INA1–
INA2+
INA2–
INSELA
INB1+
INB1–
INB2+
INB2–
INSELB
INC1+
INC1–
INC2+
INC2–
INSELC
IND1+
IND1–
IND2+
IND2–
INSELD
Character-Rate Clock
Clock &
Data
Recovery
PLL
Shifter
Clock &
Data
Recovery
PLL
Shifter
Clock &
Data
Recovery
PLL
Shifter
Clock &
Data
Recovery
PLL
Shifter
LFID
LFIC
LFIB
LFIA
8
RXSTC[2:0]
RXDC[7:0]
RXOPC
3
8
RXSTB[2:0]
RXDB[7:0]
RXOPB
3
8
RXSTD[2:0]
RXDD[7:0]
RXOPD
3
8
RXSTA[2:0]
RXDA[7:0]
RXOPA
3
Receive
Signal
Monitor
Receive
Signal
Monitor
Receive
Signal
Monitor
Receive
Signal
Monitor
Output
Register
Output
Register
Output
Register
Output
Register
Elasticity
Buffer
Framer
RXCLKD+
RXCLKD–
10B/8B
BIST
Elasticity
Buffer
10B/8B
BIST
Framer
Elasticity
Buffer
10B/8B
BIST
Framer
Elasticity
Buffer
10B/8B
BIST
Framer
÷2
RXCLKC+
RXCLKC–
÷2
RXCLKB+
RXCLKB–
÷2
RXCLKA+
RXCLKA–
÷2
RXRATE
FRAMCHAR
RFMODE
RFEN
SDASEL
JTAG
Boundary
Scan
Controller
TDO
TMS
TCLK
TDI
Clock
Select
Clock
Select
Clock
Select
Clock
Select
RXCKSEL
TRSTZ
DECMODE
Receive Path Block Diagram
= Internal Signal
RX PLL Enable
Latch
RXLE
BRE[3:0]
BIST Enable
Latch
BRE[3:0]
BISTLE
TRGRATE
SPDSEL
TRGCLK+
TRGCLK–
Clock Multiplier
PARCTL
[+] Feedback
PRELIMINARY
CYP15G0401RB
Document #: 38-02111 Rev. ** Page 5 of 35
Pin Configuration
(Top View)
[1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
INC1- N/C INC2- N/C V
CC
IND1- N/C GND IND2- N/C INA1- N/C GND INA2- N/C V
CC
INB1- N/C INB2- N/C
B
INC1+ N/C INC2+ N/C V
CC
IND1+ N/C GND IND2+ N/C INA1+ N/C GND INA2+ N/C V
CC
INB1+ N/C INB2+ N/C
C
TDI TMS INSELC INSELB V
CC
PAR
CTL
SDA
SEL
GND N/C N/C N/C N/C GND N/C GND V
CC
TRG
RATE
RX
RATE
GND TDO
D
TCLK TRSTZ INSELD INSELA V
CC
RF
MODE
SPD
SEL
GND BRE[3] BRE[2] BRE[1] BRE[0] GND N/C GND V
CC
V
CC
RXLE RFEN N/C
E
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
F
N/C V
CC
V
CC
RXCK
SEL
BISTLE RXSTB
[1]
RXOPB RXSTB
[0]
G
GNDGNDGNDGND DEC
MODE
GND FRAM
CHAR
RXDB
[1]
H
GNDGNDGNDGND GNDGNDGNDGND
J
GNDGNDGNDGND RXSTB
[2]
RXDB
[0]
RXDB
[5]
RXDB
[2]
K
RXDC
[2]
RXCLK
C–
GND LFIC RXDB
[3]
RXDB
[4]
RXDB
[7]
RXCLK
B+
L
RXDC
[3]
RXCLK
C+
GND GND RXDB
[6]
LFIB RXCLK
B–
GND
M
RXDC
[4]
RXDC
[5]
RXDC
[7]
RXDC
[6]
GNDGNDGNDGND
N
GNDGNDGNDGND GNDGNDGNDGND
P
RXDC
[1]
RXDC
[0]
RXSTC
[0]
RXSTC
[1]
GNDGNDGNDGND
R
RXSTC
[2]
RXOP
C
N/C V
CC
V
CC
V
CC
V
CC
N/C
T
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
U
V
CC
V
CC
V
CC
V
CC
V
CC
RXDD
[2]
RXDD
[1]
GND RX
OPD
N/C TRG
CLK-
GND GND GND V
CC
V
CC
RXDA
[2]
RXOPA RXSTA
[2]
RXSTA
[1]
V
V
CC
V
CC
V
CC
RXDD
[6]
V
CC
RXDD
[3]
RXSTD
[0]
GND RXSTD
[2]
N/C TRG
CLK+
N/C GND GND V
CC
V
CC
RXDA
[7]
RXDA
[3]
RXDA
[0]
RXSTA
[0]
W
V
CC
V
CC
LFID RXCLK
D–
V
CC
RXDD
[4]
RXSTD
[1]
GND N/C GND GND GND GND GND V
CC
V
CC
LFIA RXCLK
A-
RXDA
[4]
RXDA
[1]
Y
V
CC
V
CC
RXDD
[7]
RXCLK
D+
V
CC
RXDD
[5]
RXDD
[0]
GND N/C N/C GND N/C GND GND V
CC
V
CC
V
CC
RXCLK
A+
RXDA
[6]
RXDA[
5]
Note:
1. N/C = Do Not Connect
[+] Feedback
PRELIMINARY
CYP15G0401RB
Document #: 38-02111 Rev. ** Page 6 of 35
Pin Configuration
(Bottom View)
[1]
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
N/C INB2- N/C INB1- V
CC
N/C INA2- GND N/C INA1- N/C IND2- GND N/C IND1- V
CC
N/C INC2- N/C INC1-
A
N/C INB2+ N/C INB1+ V
CC
N/C INA2+ GND N/C INA1+ N/C IND2+ GND N/C IND1+ V
CC
N/C INC2+ N/C INC1+
B
TDO GND RX
RATE
TRG
RATE
V
CC
GND N/C GND N/C N/C N/C N/C GND SDA
SEL
PAR
CTL
V
CC
INSELB INSELC TMS TDI
C
N/C RFEN RXLE V
CC
V
CC
GND N/C GND BRE[0] BRE[1] BRE[2] BRE[3] GND SPD
SEL
RF
MODE
V
CC
INSELA INSELD TRSTZ TCLK
D
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
E
RXSTB
[0]
RXOP
B
RXSTB
[1]
BISTLE RXCK
SEL
V
CC
V
CC
N/C
F
RXDB
[1]
FRAM
CHAR
GND DEC
MODE
GND GND GND GND
G
GND GND GND GND GND GND GND GND
H
RXDB
[2]
RXDB
[5]
RXDB
[0]
RXSTB
[2]
GND GND GND GND
J
RXCLK
B+
RXDB
[7]
RXDB
[4]
RXDB
[3]
LFIC GND RXCLK
C-
RXDC
[2]
K
GND RXCLK
B-
LFIB RXDB
[6]
GND GND RXCLK
C+
RXDC
[3]
L
GND GND GND GND RXDC
[6]
RXDC
[7]
RXDC
[5]
RXDC
[4]
M
GND GND GND GND GND GND GND GND
N
GND GND GND GND RXSTC
[1]
RXSTC
[0]
RXDC
[0]
RXDC
[1]
P
N/C V
CC
V
CC
V
CC
V
CC
N/C RXOP
C
RXSTC
[2]
R
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
T
RXSTA
[1]
RXSTA
[2]
RXOPA RXDA
[2]
V
CC
V
CC
GND GND GND TRG
CLK-
N/C RXOP
D
GND RXDD
[1]
RXDD
[2]
V
CC
V
CC
V
CC
V
CC
V
CC
U
RXSTA
[0]
RXDA
[0]
RXDA
[3]
RXDA
[7]
V
CC
V
CC
GND GND N/C TRG
CLK+
N/C RXSTD
[2]
GND RXSTD
[0]
RXDD
[3]
V
CC
RXDD
[6]
V
CC
V
CC
V
CC
V
RXDA
[1]
RXDA
[4]
RXCLK
A-
LFIA V
CC
V
CC
GND GND GND GND GND N/C GND RXSTD
[1]
RXDD
[4]
V
CC
RXCLK
D–
LFID V
CC
V
CC
W
RXDA
[5]
RXDA
[6]
RXCLK
A+
V
CC
V
CC
V
CC
GND GND N/C GND N/C N/C GND RXDD
[0]
RXDD
[5]
V
CC
RXCLK
D+
RXDD
[7]
V
CC
V
CC
Y
[+] Feedback
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

CYP15G0401RB-BGXC

Mfr. #:
Buy CYP15G0401RB-BGXC
Manufacturer:
Cypress Semiconductor
Description:
IC RECEIVER HOTLINK 256LBGA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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