© Semiconductor Components Industries, LLC, 2012
March, 2012 Rev. P1
1 Publication Order Number:
NCP6132A/D
NCP6132A, NCP6132B
Product Preview
Dual Output 3 Phase & 2
Phase Controller with
Single SVID Interface for
Desktop and Notebook CPU
Applications
The NCP6132A/NCP6132B dual output three plus two phase buck
solution is optimized for Intel IMVP7 and VR12 compatible CPUs.
The controller combines true differential voltage sensing, differential
inductor DCR current sensing, input voltage feedforward, and
adaptive voltage positioning to provide accurately regulated power for
both Desktop and Notebook applications. The control system is based
on DualEdge pulsewidth modulation (PWM) combined with DCR
current sensing providing the fastest initial response to dynamic load
events and reduced system cost. It also sheds to single phase during
light load operation and can auto frequency scale in light load while
maintaining excellent transient performance.
There are three internal MOSFET drivers inside the chip. One of
these three integrated driver can be configured either to drive core
phase or aux phase. NCP6132A and NCP6132B have almost same
structure except that NCP6132A has two integrated drivers for the
core rail and one integrated driver for auxiliary rail, while the
NCP6132B has all three integrated drivers for the core rail.
Features
Meets Intel’s VR12/IMVP7 Specifications
Three Phase CPU Voltage Regulator, and Two Phase Auxiliary
Voltage Regulator, with Three Internal MOSFET Drivers in Total
Current Mode Dual Edge Modulation for Fastest Initial Response to
Transient Loading
Dual High Performance Operational Error Amplifier
One Digital Soft Start Ramp for Both Rails
Dynamic Reference Injection
Accurate Total Summing Current Amplifier
DAC with Droop Feedforward Injection
Dual High Impedance Differential Voltage and Total
Current Sense Amplifiers
PhasetoPhase Dynamic Current Balancing
“Lossless” DCR Current Sensing for Current Balancing
Summed Thermally Compensated Inductor Current
Sensing for Droop
True Differential Current Balancing Sense Amplifiers
for Each Phase
Adaptive Voltage Positioning (AVP)
Vin Feed Forward Ramp Slope
Pin Programming for Internal SVID Parameters
Over Voltage Protection (OVP) & Under Voltage
Protection (UVP)
Over Current Protection (OCP)
Dual Power Good Output with Internal Delays
Pbfree and Halidefree Packages are Available
Applications
Desktop & Notebook Processors
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
QFN60
CASE 485BB
MARKING
DIAGRAM
http://onsemi.com
160
NCP6132x
AWLYYWWG
1
x = A or B
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
Device Package Shipping
ORDERING INFORMATION
NCP6132AMNR2G
QFN60
(PbFree)
2500/Tape
& Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NCP6132BMNR2G
NCP6132A, NCP6132B
http://onsemi.com
2
AUX
PWM
GENERATOR
MAIN
CURRENT
BALANCE
DATA
REGISTERS
SVID
INTERFACCE
AUX OVP
THERMAL
MONITOR
UVLO & EN
EN
GND
VCC
AUX VR READY
COMPARATOR
ENABLE
ENABLE
VSPA
VSNA
DACA
DROOPA
VR READY
COMPARATOR
ENABLE
VSP
VSN
DAC
DROOP
VRDYA
VRDY
TSNS
TSNSA
VRHOT#
VSPA
VSNA
OVPA
OVP
VSP
VSN
OVP
SDIO
SCLK
ALERT#
ENABLE
ADC
VSPA VSNA
VSP VSN
TSNS
TSNSA
IMON
IMONA
IMAX
IMAXA
MUX
VSP
VSN
DROOP
DAC
GND
CSREF
1.3 V
DIFFAMP
DIFF
DAC
AUX
DAC
DAC
AUX
DAC
FB
1.3 V
+
COMP
ERROR
AMP
TRBST
DETECT
TRBST#
+
CS
AMP
CSSUM
CSREF
CSCOMP
IOUT
ILIM
ILIM
IOUT
CSP1
CSP2
CSP3
CSREF
CORE PHASE
GENERATOR
LG1
HG1
LG2
HG2
PVCC
PGND
PGND
BST1
SW1
PVCC
BST2
SW2
PWM
DRVEN
ENABLE
COMP
OVP
RAMP
GENERATORS
VRMP
ROSC
ENABLE
VSPA
VSNA
DROOPA
GND
CSREFA
1.3 V
AUX
DIFFAMP
DIFFA
HGA
BSTA
SWA
LGA
PGND
PVCC
PWMA
AUX
CURRENT
BALANCE
CSP1A
CSP2A
CSREFA
RAMP1
RAMP2
RAMP3
RAMPA1
RAMPA2
AUX
DAC
+
CSSUMA
CSREFA
CSCOMPA
IOUTA
ILIMA
ILIMA
IOUTA
AUX
CS
AMP
FBA
1.3 V
+
COMPA
AUX
ERROR
AMP
TRBSTA
DETECT
ENABLE
COMPA
OVPA
TRBSTA#
VBOOT
VDDBP
Figure 1. Block Diagram
NCP6132A, NCP6132B
http://onsemi.com
3
ROSC
VRMP
VRDY
ILIM
SCLK
VRHOT#
SDIO
ALERT#
FBA
TRBST#
VCC
SW1
HG1
DIFFA
COMPA
CSSUMA
CSREFA
CSP2A
CSCOMPA
ILIMA
PWM
BST1
CSP1A
VSNA
VDDBP
VSPA
DRVEN
VSP
CSP1
CSREF
CSCOMP
CSP2
DROOPA
IOUT
BSTA
PVCC
HGA
SWA
LGA
BST2
HG2
SW2
LG2
COMP
CSSUM
PGND
VSN
FB
LG1
CSP3
VBOOT
PWMA
DIFF
EN
Tab: GND
IOUTA
VRDYA
1
60
15
16
46
45
31
30
NCP6132A/NCP6132B
DROOP
TSNSA
TSNS
TRBSTA#
Figure 2. QFN60 Pin Diagram
Table 1. QFN60 PIN LIST DESCRIPTION
Pin
No.
Symbol Description
1 VCC Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground.
2 VDDBP
Digital Logic power. Connect this pin to VCC with 10 W. Connect 0.1 mF capacitor from this pin to
ground
3 VRDYA Open drain output. High indicates that the aux output is regulating.
4 EN Logic input. Logic high enables both outputs and logic low disables both outputs.
5 SDIO Serial VID data interface.
6 ALERT# Serial VID ALERT#.
7 SCLK Serial VID clock.
8 VBOOT A resistor to GND on this pin sets the Core and Aux Bootup Voltage
9 ROSC A resistance from this pin to ground programs the oscillator frequency. This pin supplies a trimmed
output voltage of 2 V.
10 VRMP Feedforward input of Vin for the ramp slope compensation. The current fed into this pin is used to
control of the ramp of PWM slope
11 VRHOT# Thermal logic output for over temperature.
12 VRDY Open drain output. High indicates that the core output is regulating.
13 VSN Inverting input to the core differential remote sense amplifier.
14 VSP Noninverting input to the core differential remote sense amplifier.
15 DIFF Output of the core differential remote sense amplifier.
16 TRBST# Compensation pin for the load transient boost.
17 FB Error amplifier voltage feedback for core output
18 COMP Output of the error amplifier and the inverting inputs of the PWM comparators for the core output.
19 IOUT Total output current monitor for core output. Short it to GND if IMON function is not needed.
20 ILIM Over current shutdown threshold setting for core output. Resistor to CSCOMP to set threshold.
21 DROOP Used to program droop function for core output. It’s connected to the resistor divider placed between
CSCOMP and CSREF summing node.
22 CSCOMP Output of total current sense amplifier for core output.

NCP6132AMNR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers 3 + 2 CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
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