NCP6132A, NCP6132B
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PROTECTION FEATURES
Input Under Voltage Protection
NCP6132A/NCP6132B monitors the 5 V VCC supply
and the VRMP pin for under voltage protection. The gate
driver monitors both the gate driver VCC and the BST
voltage. When the voltage on the gate driver is insufficient
it will pull HG1, HG2, HGA, LG1, LG2, LGA, DRVEN low
and notify the controller the power is not ready. The gate
driver will hold HG1, HG2, HGA, LG1, LG2, LGA,
DRVEN low for a minimum period of time to allow the
controller to restart its startup sequence. In this case the
PWM and PWMA are set back to the MID state and soft start
would begin again. See the figure below.
DAC
Gate Driver Pulls DRVEN
Low during driver UVLO
and Calibration
If DRVEN is pulled low the
controller will hold off its
startup
Figure 15. Gate Driver UVLO Restart
Soft Start
Soft start is implemented internally. A digital counter
steps the DAC up from zero to the target voltage based on the
predetermined slew rate in the spec table. The PWM signals
will start out open with a test current to collect data on
IMAX/IMAXA and for setting internal registers. After the
IMAX/IMAXA configuration data is collected the
controller enables and sets the PWM signal to the 2.0 V MID
state to indicate that the drivers should be in diode mode.
DRVON will then be asserted and the COMP pin released to
begin soft−start. The DAC will ramp from Zero to the target
DAC codes and the PWM outputs will begin to fire. Each
phase will move out of the MID state when the first PWM
pulse is produced preventing the discharge of a pre−charged
output.
Figure 16. Soft−Start Sequence
Over Current Latch− Off Protection
The NCP6132A/NCP6132B provides two different types
of current limit protection. During normal operation a
programmable total current limit is provided that scales with
the phase count during power saving operation. A second
fixed per−phase current limit is provided for VID lower than
0.25 V, such as during soft−start.
The level of total current limit is set with the resistor from
the ILIM pin to CSCOMP pin. Internally the current through
ILIM pin is scaled and then compared to two current
thresholds 10 mA and 15 mA, where 10 mA threshold is
scaled to indicate the 100% current limit and 15 mA
indicates the 150% current limit. If 100% current limit is
exceeded, an internal latch−off counter starts. The controller
shuts down if the over current fault is not removed after
50 ms. If 150% current limit is exceeded, the controller shuts
down immediately. To recover from an OCP fault the EN pin
must be cycled low. The current limit is scaled down along
with the phase shedding. Phase shedding from 3−phase to
single phase scales the current limit to its 1/3; phase
shedding from 2−phase to single phase scales the current
limit to its half. For example, for a 3−phase design in PS0
state the 100% current limit trips if ILIM current exceeds
10 mA, but in PS1/2/3 state (phase shedding to single phase)
ILIM current above 3.3 mA will trigger the 100% current
limit.
Under Voltage Monitor
The output voltage is monitored at the output of the
differential amplifier for UVLO. If the output falls more
than 300 mV below the DAC−DROOP voltage the UVLO
comparator will trip sending the VRDY/VRDYA signal low.
