NCP6132A, NCP6132B
http://onsemi.com
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SVID Addressing
The NCP6132A/NCP6132B has fixed SVID device
addresses for core and aux rail. The core rail address is 0000,
and aux rail address is 0001.
Remote Sense Amplifier
A high performance high input impedance true
differential amplifier is provided to accurately sense the
output voltage of the regulator. The VSP and VSN inputs
should be connected to the regulator’s output voltage sense
points. The remote sense amplifier takes the difference of
the output voltage with the DAC voltage and adds the droop
voltage to
V
DIFF
+
ǒ
V
VSP
* V
VSN
Ǔ
)
ǒ
1.3 V * V
DAC
Ǔ
(eq. 1)
)
ǒ
V
DROOP
* V
CSREF
Ǔ
This signal then goes through a standard error
compensation network and into the inverting input of the
error amplifier. The non−inverting input of the error
amplifier is connected to the same 1.3 V reference used for
the differential sense amplifier output bias.
High Performance Voltage Error Amplifier
A high performance error amplifier is provided for high
bandwidth transient performance. A standard type 3
compensation circuit is normally used to compensate the
system.
Differential Current Feedback Amplifiers
Each phase has a low offset differential amplifier to sense
that phase current for current balance and per phase OCP
protection during soft−start. The inputs to the CSREF and
CSPx pins are high impedance inputs. It is recommended
that any external filter resistor RCSN not exceed 10 kW to
avoid offset issues with leakage current. It is also
recommended that the voltage sense element be no less than
0.5 mW for accurate current balance. Fine tuning of this time
constant is generally not required.
CCSN
RCSN
DCR
LPHASE
12
SWNx
VOUT
CSPx
CSREF
R
CSN
+
L
PHASE
C
CSN
*DCR
Figure 8.
The individual phase current is summed into to the PWM
comparator feedback in this way current is balanced is via
a current mode control approach.
Total Current Sense Amplifier
The NCP6132A/NCP6132B uses a patented approach to
sum the phase currents into a single temperature
compensated total current signal. This signal is then used to
generate the output voltage droop, total current limit, and the
output current monitoring functions. The total current signal
is floating with respect to CSREF. The current signal is the
difference between CSCOMP and CSREF. The Ref(n)
resistors sum the signals from the output side of the
inductors to create a low impedance virtual ground. The
amplifier actively filters and gains up the voltage applied
across the inductors to recover the voltage drop across the
inductor series resistance (DCR). Rth is placed near an
inductor to sense the temperature of the inductor. This
allows the filter time constant and gain to be a function of the
Rth NTC resistor and compensate for the change in the DCR
with temperature.
Figure 9.
-
+
CSN1
CSN2
CSN3
SWN1
SWN2
SWN3
1n
Cref
CSREF
CSSUM
CSCOMP
Rref1
Rref2
Rref3
Rph1
Rph2
Rph3
Ccs1
Ccs2
Rth
Rcs1Rcs2
The DC gain equation for the current sensing:
V
CSCOMP−CSREF
+
Rcs2 )
Rcs1*Rth
Rcs1)Rth
Rph
(eq. 2)
*
ǒ
Iout
Total
* DCR
Ǔ
Set the gain by adjusting the value of the Rph resistors.
The DC gain should set to the output voltage droop. If the
voltage from CSCOMP to CSREF is less than 100 mV at
ICCMAX then it is recommended to increase the gain of the
CSCOMP amp and add a resister divider to the Droop pin
filter. This is required to provide a good current signal to
offset voltage ratio for the ILIM pin. When no droop is
needed, the gain of the amplifier should be set to provide
~100 mV across the current limit programming resistor at
full load. The values of Rcs1 and Rcs2 are set based on the
220k NTC and the temperature effect of the inductor and
should not need to be changed. The NTC should be placed
near the closest inductor. The output voltage droop should
be set with the droop filter divider.
The pole frequency in the CSCOMP filter should be set
equal to the zero from the output inductor. This allows the
circuit to recover the inductor DCR voltage drop current
