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NCP6132AMNR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
NCP6132A, NCP6132B
http://onsemi.com
4
Table 1. QFN60 PIN LIST DESCRIPTION
Pin
No.
DescriptionSymbol
23 CSSUM Inverting input of total current sense amplifier for core output.
24 CSREF Total output current sense amplifier reference voltage input. And inverting input to core current bal-
ance sense amplifiers.
25 CSP3 Non−inverting input to current balance sense amplifier for phase 3
26 CSP2 Non−inverting input to current balance sense amplifier for phase 2
27 CSP1 Non−inverting input to current balance sense amplifier for phase 1
28 TSNS Temp Sense input for the core converter.
29 DRVEN Bidirectional gate driver enable for external drivers for both core and aux rails. It should be left floating
if unused.
30 PWM Phase 3 PWM output. A resistor to ground on this pin programs IMAX.
31 BST1 High−Side Bootstrap supply for phase 1
32 HG1 High−Side gate drive output for phase 1
33 SW1 Current return for high−side gate drive for phase 1
34 LG1 Low−Side gate drive output for phase 1
35 PGND Power ground for gate drivers
36 PVCC Power Supply for gate drivers
37 LG2 Low−Side gate drive output for phase 2
38 SW2 Current return for high−side gate drive for phase 2
39 HG2 High−Side gate drive output for phase 2
40 BST2 High−Side Bootstrap supply for phase 2
41 LGA Low−Side gate drive output for aux phase 1
42 SWA Current return for high−side gate drive for aux phase 1
43 HGA High−Side gate drive output for aux phase 1
44 BSTA High−Side Bootstrap supply for aux phase 1
45 PWMA Aux Phase 2 PWM output. A resistor to ground on this pin programs IMAXA.
46 TSNSA Temp sense for the aux converter
47 CSP1A Non−inverting input to aux current balance sense amplifier for phase 1
48 CSP2A Non−inverting input to aux current balance sense amplifier for phase 2
49 CSREFA Total output current sense amplifier reference voltage input for aux. Inverting input to aux current
balance sense amplifier for phase 1 and 2
50 CSSUMA Inverting input of total current sense amplifier for aux output
51 CSCOMPA Output of total current sense amplifier for aux output
52 DROOPA Used to program droop function for aux output. It’s connected to the resistor divider placed between
CSCOMPA and CSREFA.
53 ILMA Over current shutdown threshold setting for aux output. Resistor to CSCOMPA to set threshold.
54 IOUTA Total output current monitor for aux output. Short to GND if IMON function is not needed.
55 COMPA Output of aux error amplifier and inverting input of PWM comparator for aux output
56 FBA Error amplifier voltage feedback for aux output
57 TRBSTA# Compensation pin for load transient boost
58 DIFFA Output of the aux differential remote sense amplifier
59 VSPA Non−inverting input to aux differential remote sense amplifier
60 VSNA Inverting input to aux differential remote sense amplifier
61 GND Analog ground
NCP6132A, NCP6132B
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5
ABSOLUTE MAXIMUM RATINGS
Table 2. ELECTRICAL INFORMATION
Pin Symbol V
MAX
V
MIN
I
SOURCE
I
SINK
COMP, COMPA V
CC
+ 0.3 V −0.3 V 2 mA 2 mA
CSCOMP, CSCOMPA V
CC
+ 0.3 V −0.3 V 2 mA 2 mA
VSN, VSNA GND + 300 mV GND – 300 mV 1 mA 1 mA
DIFF, DIFFA V
CC
+ 0.3 V −0.3 V 2 mA 2 mA
VRDY, VRDYA V
CC
+ 0.3 V −0.3 V N/A 2 mA
VDDPB, VCC, PVCC 6.5 V −0.3 V N/A N/A
ROSC V
CC
+ 0.3 V −0.3 V 1 mA N/A
IOUT, IOUTA Output TBD −0.3 V
VRMP +25 V −0.3 V
SW1, SW2, SWA 28 V −5 V
−10 V ≤ 200 ns
BST1, BST2, BSTA 34 V wrt/ GND
6.5 V wrt/ SW
−0.3 V wrt/ SW
LG1, LG2, LGA V
CC
+ 0.3 V −0.3 V
−5 V ≤ 200 ns
HG1, HG2, HGA BST + 0.3 V −0.3 V wrt/ SW
−2 V ≤ 200 ns wrt/ SW
All Other Pins V
CC
+ 0.3 V −0.3 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*All signals referenced to GND unless noted otherwise.
Table 3. THERMAL INFORMATION
Parameters Symbol Typical Units
Thermal Characteristic
QFN Package (Note 1)
R
JA
31
_C/W
Operating Junction Temperature Range (Note 2) T
J
−10 to +125
_C
Operating Ambient Temperature Range −10 to +100
_C
Maximum Storage Temperature Range T
STG
−40 to +150
_C
Moisture Sensitivity Level
QFN Package
MSL 1
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
NCP6132A, NCP6132B
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6
Table 4. NCP6132A/NCP6132B (3+2) ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < T
A
< 100°C; V
CC
= 5.0 V; C
VCC
= 0.1 mF
Parameter
Test Conditions Min Typ Max Units
ERROR AMPLIFIER
Input Bias Current −400 400 nA
Open Loop DC Gain CL = 20 pF to GND,
RL = 10 kW to GND
80 dB
Open Loop Unity Gain Bandwidth CL = 20 pF to GND,
RL = 10 kW to GND
55 MHz
Slew Rate
DV
in
= 100 mV, G = −10 V/V,
DV
out
= 1.5 V – 2.5 V,
C
L
= 20 pF to GND,
DC Load = 10k to GND
20
V/ms
Maximum Output Voltage I
SOURCE
= 2.0 mA 3.5 − − V
Minimum Output Voltage I
SINK
= 2.0 mA − − 1 V
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current −400 − 400 nA
VSP Input Voltage Range −0.3 − 3.0 V
VSN Input Voltage Range −0.3 − 0.3 V
−3 dB Bandwidth C
L
= 20 pF to GND,
R
L
= 10 kW to GND
12 MHz
Closed Loop DC gain VS to DIFF VS+ to VS− = 0.5 to 1.3 V 1.0 V/V
Droop Accuracy CSREF − DROOP = 80 mV
DAC = 0.8 V to 1.2 V
−10°C ~ 100°C
−10°C ~ 85°C
78.5
79
81.5
81
mV
Maximum Output Voltage I
SOURCE
= 2 mA 3.0 − − V
Minimum Output Voltage I
SINK
= 2 mA − − 0.5 V
3. Guaranteed by design/characterization, not in production test
4. Guaranteed by characterization
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

NCP6132AMNR2G

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Buy NCP6132AMNR2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers 3 + 2 CONTROLLER
Lifecycle:
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