ADP3207JCPZ-RL Datasheet ADP3207JCPZ-RL | P13-P15

ADP3207

Rev. 1 | Page 13 of 29 | www.onsemi.com

node side of the output inductors) are summed together by

using series summing resistors. The feedback resistor between

CSCOMP and CSSUM sets the gain of the current-sense

amplifier, and a filter capacitor is placed in parallel with this

resistor. The current information is then given as the voltage

difference between CSREF and CSCOMP. This signal is used

internally as a differential input for the current-limit

comparator.

An additional resistor divider connected between CSREF and

CSCOMP with the midpoint connected to LLSET can be used

to set the load line required by the microprocessor specification.

The current information for load line setting is then given as

the voltage difference of CSREF − LLSET. The configuration in

the previous paragraph makes it possible for the load line slope

to be set independently of the current-limit threshold. In the

event that the current-limit threshold and load line do not have

to be independent, the resistor divider between CSREF and

CSCOMP can be omitted and the CSCOMP pin can be

connected directly to LLSET. To disable voltage positioning

entirely (that is, to set no load line), tie LLSET to CSREF.

To provide the best accuracy for current sensing, the CSA is

designed to have a low offset input voltage. In addition, the

sensing gain is set by an external resistor ratio.

ACTIVE IMPEDANCE CONTROL MODE

To control the dynamic output voltage droop as a function of

the output current, the signal proportional to the total output

current is converted to a voltage that appears between CSREF

and LLSET. This voltage can be scaled to equal the droop voltage,

which is calculated by multiplying the droop impedance of the

regulator with the output current. The droop voltage is then

used as the control voltage of the PWM regulator. The droop

voltage is subtracted from the DAC reference output voltage

and determines the voltage positioning setpoint. The setup

results in an enhanced feed-forward response.

CURRENT CONTROL MODE AND THERMAL

BALANCE

The ADP3207 has individual inputs for monitoring the current in

each phase. The phase current information is combined with an

internal ramp to create a current balancing feedback system

that is optimized for initial current accuracy and dynamic

thermal balance. The current balance information is

independent of the total inductor current information used for

voltage positioning described in the Active Impedance Control

Mode section.

The magnitude of the internal ramp can be set so the transient

response of the system becomes optimal. The ADP3207 also

monitors the supply voltage to achieve feed-forward control

whenever the supply voltage changes. A resistor connected from

the power input voltage rail to the RAMPADJ pin determines

the slope of the internal PWM ramp. Detailed information

about programming the ramp is given in the Ramp Resistor

Selection section.

External resistors can be placed in series with the SW2 and

SW3 pins to create an intentional current imbalance, if desired.

Such a condition can exist when one phase has better cooling

and supports higher currents than the other phase. Resistor

RSW2 and Resistor RSW3 (see the typical application circuit in

Figure 10) can be used to adjust thermal balance. It is

recommended to add these resistors during the initial design to

make sure placeholders are provided in the layout.

To increase the current in any given phase, users should make

RSW for that phase larger (that is, make RSW = 0 for the hottest

phase and do not change it during balance optimization).

Increasing RSW to 500 Ω makes a substantial increase in phase

current. Increase each RSW value by small amounts to achieve

thermal balance starting with the coolest phase.

When current limit is reached, the ADP3207 switches to full-

phase PWM mode, regardless of System Signal DRPSLP and

PSI

to avoid inrush current stress to the Phase 1 power stage.

VOLTAGE CONTROL MODE

A high gain bandwidth error amplifier is used for the voltage-

mode control loop. The noninverting input voltage is set via the

7-bit VID DAC. The VID codes are listed in Table 6. The

noninverting input voltage is offset by the droop voltage as a

function of current, commonly known as active voltage

positioning. The output of the error amplifier is the COMP pin,

which sets the termination voltage for the internal PWM ramps.

The negative input, FB, is tied to the output sense location

through a resistor, RB, for sensing and controlling the output

voltage at the remote sense point. The main loop compensation

is incorporated in the feedback network connected between FB

and COMP.

POWER-GOOD MONITORING

The power-good comparator monitors the output voltage via

the CSREF pin. The PWRGD pin is an open drain output that

can be pulled up through an external resistor to a voltage rail

that is not necessarily the same VCC voltage rail of the

controller. Logic high level indicates that the output voltage is

within the voltage limits defined by a window around the VID

voltage setting. PWRGD goes low when the output voltage is

outside of that window.

Following the IMVP-6 specification, PWRGD window is

defined as −300 mV below and +200 mV above the actual VID

DAC output voltage. For any DAC voltage below 300 mV, only

the upper limit of the PWRGD window is monitored. To

prevent false alarm, the power-good circuit is masked during

various system transitions, including any VID change and

entrance/exit out of deeper sleep. The duration of the PWRGD

ADP3207

Rev. 1 | Page 14 of 29 | www.onsemi.com

mask is set by an internal timer to be about 100 µs. In

conditions where a larger than 200 mV voltage drop occurs

during deeper sleep entry or slow deeper sleep exit, the

duration of PWRGD masking is extended by an internal logic

circuit.

POWER-UP SEQUENCE AND SOFT START

The power-on ramp-up time of the output voltage is set with a

capacitor tied from the SS pin to GND. The capacitance on the

SS pin also determines the current-limit latch-off time as

explained in the Soft Transient section. The whole power-up

sequence, including soft start, is illustrated in Figure 9.

In VCC UVLO or in shutdown, the SS pin is held at zero

potential. When VCC ramps above the upper UVLO threshold

and EN is asserted high, the ADP3207 enables internal bias and

starts a reset cycle that lasts about 50 μs to 60 µs. Next, when

initial reset is over, the chip detects the number of phases set by

the user, and gives a go signal to ramp up the SS voltage. During

soft start, the external SS capacitor is charged by an internal

8 µA current source. The V

CORE

voltage follows the ramping SS

voltage up to the V

BOOT

voltage level, which is determined by a

burnt-in VID code (the 1.2 V code by IMVP-6 specification).

While V

CORE

is being regulated at V

BOOT

voltage, the SS capacitor

continues to rise. When the SS pin voltage reaches 1.7 V, the

ADP3207 asserts the

CLKEN

signal low, given that the V

CORE

voltage is within the power-good window of V

BOOT

. The

ADP3207 reads the VID codes provided by the CPU on VID0

to VID6 input pins. The V

CORE

voltage changes from V

BOOT

the VID voltage by a well controlled soft transition, as

introduced in the Soft Transient section. Meanwhile, the SS pin

voltage is quickly charged up to a clamp voltage of 2.9 V.

The PWRGD signal is not asserted until there is a t

CPU_PWRGD

delay of about 3 ms to 10 ms as specified by the IMVP-6. The

power-good delay can be programmed by the capacitor

connected from PGDELAY to GND. Before the

CLKEN

signal

is asserted low, PGDELAY is reset to zero. After the assertion of

the

CLKEN

signal, an internal source current of 2 µA starts

charging up the external capacitor on the PGDELAY pin.

Assuming the V

CORE

voltage is settled within the power-good

window defined by the VID DAC voltage, the PWRGD signal is

asserted high when the PGDELAY voltage reaches the 2.9 V

power-good delay termination threshold.

If either EN is taken low or VCC drops below the lower VCC

UVLO threshold, then both the SS capacitor and PGDELAY

capacitor are reset to ground to be ready for another soft-start cycle.

VCC

CLKEN

PWRGD

CORE

CPU_PWRGD

VID

BOOT

1.2V

1.7V

2.9V

05782-009

Figure 9. Power-Up Sequence

SOFT TRANSIENT

The ADP3207 provides a soft transient function to reduce inrush

current during various transitions, including the entrance/exit of

deeper sleep and the transition from V

BOOT

to VID voltage.

Reducing the inrush current helps decrease the acoustic noise

generated by the MLCC input capacitors and inductors.

The soft transient feature is implemented with an STSET buffer

amplifier that outputs constant sink or source current on the

STSET pin where an external capacitor is connected. The

capacitor is used to program the slew rate of V

CORE

voltage

during any VID voltage transient. During steady-state

operation, both the reference input of the voltage error

amplifier and the STSET amplifier are connected to the VID

DAC output. Consequently, the STSET voltage is a buffered

version of VID DAC output. When system signals trigger a soft

transition, the reference input of the voltage error amplifier

switches from the DAC output to the STSET output, while the

input of the STSET amplifier remains connected to the DAC.

The STSET buffer input sees the almost instantaneous VID

voltage change and tries to track it. Tracking is not

instantaneous because the buffer slew rate is limited by the

source/sink current capability of the STSET output. Therefore,

CORE

voltage follows the VID DAC output voltage change with

a controlled slew rate. When the transient period is complete,

the reference input of the voltage amplifier switches back to the

VID DAC output to ensure higher accuracy.

ADP3207

Rev. 1 | Page 15 of 29 | www.onsemi.com

Table 5 lists the source/sink current on the STSET pin for

various transitions. By charging/discharging the external

capacitor on the STSET pin, users actually program the voltage

slew rate on the STSET pin, and consequently, on the V

CORE

output. For example, a 750 pF STSET capacitor leads to a

10 mV/s V

CORE

slew rate appropriate for a fast exit from deeper

sleep, and to a ±3.3 mV/µs V

CORE

slew rate for a slow entry to, or

exit from, deeper sleep.

Table 5. Source/Sink Current of STSET

System Signals

VID Transient

DPRSLP

DPRSTP

STSET

Current

Entrance to Deeper Sleep HIGH DNC

−2.5 ȝA

Fast Exit from Deeper Sleep LOW DNC

+7.5 ȝA

Slow Exit from Deeper Sleep HIGH HIGH +2.5 ȝA

Transient from V

BOOT

to VID DNC

DNC

±2.5 ȝA

Do not care.

CURRENT-LIMIT, SHORT-CIRCUIT, AND LATCH-

OFF PROTECTION

The ADP3207 compares the differential output of a current-

sense amplifier to a programmable current-limit setpoint to

provide current-limiting function. The nominal voltage on the

ILIMIT pin is 1.7 V. The current-limit threshold is set with a

resistor connected from the ILIMIT pin to GND. In multiphase

normal operating mode, the ILIMIT is internally scaled by

using a trimmed 12 kΩ resistor to give a current-limit threshold

of 10 mV for each µA of ILIMIT current. For single-phase

operation, the current-limit threshold is scaled down even

further. The scaling factor is the user selected number of

phases. For example, a 3-phase design scales the current-limit

threshold to 3.3 mV/µA referred to single-phase operation; a 2-

phase design scales the current-limit threshold to 5 mV/µA also

referred to single-phase operation. During any mode of

operation, if the voltage difference between CSREF and

CSCOMP rises above the current-limit threshold, the internal

current-limit amplifier takes control over the internal COMP

voltage to maintain an average output current equal to the set

limit level.

During start-up when the output voltage is below 200 mV, a

secondary current limit is activated. This is necessary because

the voltage swing on CSCOMP cannot extend below ground.

The secondary current-limit circuit clamps the internal COMP

voltage and sets the internal compensation ramp termination

voltage at 1.5 V level. The clamp actually limits voltage drop

across the low side MOSFETs through the current balance

circuitry.

An inherent per phase current limit protects individual phases

in case one or more phases stop functioning because of a faulty

component. This limit is based on the maximum normal-mode

COMP voltage.

After a current limit is hit, or following a PWRGD failure, the

SS pin is discharged by an internal sink current of 2 µA. A

comparator monitors the SS pin voltage and shuts off the

controller when the voltage drops below about 1.65 V. Because

voltage ramp (2.9 V − 1.65 V = 1.25 V) and discharge current

(2 µA) are internally fixed, current-limit latch-off delay time

can be set by selecting the external SS pin capacitor.

The controller keeps cycling the phases during latch-off delay

time. If current overload is removed and PWRGD is recovered

before the 1.65 V threshold is reached, then the controller

resumes normal operation, and the SS pin voltage recovers to

2.9 V clamp level.

The latch-off can be reset by removing and reapplying VCC, or

by recycling the EN pin low and high for a short time. To

disable the current-limit latch-off function, an external pull-up

resistor can be tied from the SS pin to the VCC rail. The pull-up

current has to override the 2 µA sink current of the SS pin to

prevent the SS capacitor from discharging down to the 1.65 V

latch-off threshold.

CHANGING VID ON-THE-FLY

The ADP3207 is designed to track dynamically changing VID

code. As a result, the converter output voltage, that is, the CPU

VCC voltage, can change without the need to reset either the

controller or the CPU. This concept is commonly referred to as

VID on-the-fly (VID OTF) transient. A VID-OTF can occur

either under light load or heavy load conditions. The processor

signals the controller by changing the VID inputs in LSB

incremental steps from the start code to the finish code. The

change can be either upwards or downwards steps.

When a VID input changes state, the ADP3207 detects the

change but ignores the new code for a minimum of time of

400 ns. This keep out is required to prevent reaction to false

code that can occur by a skew in the VID code while the 7-bit

VID input code is in transition. Additionally, the VID change

triggers a PWRGD masking timer to prevent a PWRGD failure.

Each VID change resets and retriggers the internal PWRGD

masking timer. As listed in Table 5, during any VID transient,

the ADP3207 forces a multiphase PWM mode regardless of

system input signals.

OUTPUT CROWBAR

To protect the CPU load and output components of the

converter, the PWM outputs are driven low,

DCM

and

are

driven high (that is, commanded to turn on the low-side

MOSFETs of all phases) when the output voltage exceeds an

OVP threshold of 1.7 V as specified by IMVP-6.

Turning on the low-side MOSFETs discharges the output

capacitor as soon as reverse current builds up in the inductors.

If the output overvoltage is due to a short of the high-side

MOSFET, then this crowbar action current limits the input

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