ADP3207
Rev. 1 | Page 28 of 29 | www.onsemi.com
Whenever a power-dissipating component (for example, a
power MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately
surrounding it, is recommended. Two important reasons for
this are: improved current rating through the vias, and
improved thermal performance from vias extended to the
opposite side of the PCB where a plane can more readily
transfer the heat to the air. Make a mirror image of any pad
being used to heat sink the MOSFETs on the opposite side of
the PCB to achieve the best thermal dissipation to the air
around the board. To further improve thermal performance, the
largest possible pad area should be used.
The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.
For best EMI containment, use a solid power ground plane as one
of the inner layers extending fully under all the power components.
It is important for conversion efficiency that MOSFET drivers,
such as ADP3419, are placed as close to the MOSFETs as
possible. Thick and short traces are required between the driver
and MOSFET gate, especially for the SR MOSFETs. Ground the
MOSFET driver’s GND pin through immediately close vias.
Signal Circuitry
The output voltage is sensed and regulated between the FB pin
and the FBRTN pin, which connects to the signal ground at the
load. To avoid differential mode noise pickup in the sensed
signal, the loop area should be small. Thus, route the FB and
FBRTN traces adjacent to each other atop the power ground
plane back to the controller. To filter any noise from the FBRTN
trace, using a 1000 pF MLCC is suggested. It should be placed
between the FBRTN pin and local ground and as close to the
FBRTN pin as possible.
Connect the feedback traces from the switch nodes as close as
possible to the inductor. The CSREF signal should be Kelvin
connected to the center point of the copper bar, which is the
V
CORE
common node for the inductors of all phases.
In the back side of the ADP3207 package, a metal pad can be
used as the device heat sink. In addition, running vias under the
ADP3207 is not recommended because the metal pad can cause
shorting between vias.
