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ADP3207JCPZ-RL

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ADP3207
Rev. 1 | Page 7 of 29 | www.onsemi.com
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC –0.3 V to +6 V
FBRTN –0.3 V to +0.3 V
SW1 to SW3 −10 V to +25 V
RAMPADJ (In Shutdown) –0.3 V to +25 V
All Other Inputs and Outputs –0.3 V to VCC + 0.3 V
Storage Temperature –65°C to +150°C
Operating Ambient Temperature Range 0°C to 100°C
Operating Junction Temperature 125°C
Thermal Impedance (θ
JA
)
98°C/W
Lead Temperature
Soldering (10 sec) 300°C
Infrared (15 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADP3207
Rev. 1 | Page 8 of 29 | www.onsemi.com
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10
9
8
7
6
5
4
3
2
1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
ADP3207
TOP VIEW
(Not to Scale)
EN
PWRGD
PGDELAY
FBRTN
FB
COMP
SS
STSET
DPRSLP
CLKEN
TTSENSE
VRTT
DCM
PWM2
PWM3
SW1
SW2
SW3
PWM1
OD
05782-005
VID0
VID1
VID2
VID5
VID6
DPRSTP
PSI
VCC
VID4
VID3
ILIMIT
VRPM
RRPM
RT
RAMPADJ
LLSET
CSREF
CSSUM
CSCOMP
GND
PIN 1
INDICATOR
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
2 PWRGD Power-Good Output. Open drain output that signals when the output voltage is outside of the proper operating
range. The pull-high voltage on this pin cannot be higher than VCC.
3 PGDELAY Power-Good Delay Setting Input. A capacitor between this pin and GND sets the power-good delay time.
4
CLKEN
Clock Enable Output. The pull-high voltage on this pin cannot be higher than VCC.
5 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
6 FB Feedback Input. Error amplifier input for remote sensing of the output voltage.
7 COMP Error Amplifier Output and Compensation Point.
8 SS Soft-Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft-start
ramp-up time and the current-limit latch-off delay time.
9 STSET Soft Transient Slew Rate Timing Input. A capacitor from this pin to GND sets the slew rate of the output voltage
when transitioning between the boot voltage and the programmed VID voltage, and when transitioning
between active mode and deeper sleep mode.
10 DPRSLP Deeper Sleep Control Input.
11 ILIMIT Current-Limit Setpoint. An external resistor from this pin to GND sets the current-limit threshold of the converter.
12 VRPM RPM Mode Reference Voltage Output.
13 RRPM RPM Mode Timing Control Input. A resistor between this pin and VRPM sets the RPM mode turn-on threshold voltage.
14 RT Multiphase Frequency Setting Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device when operating in multiphase PWM mode.
15 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM
ramp.
16 LLSET Output Load Line Programming Input. The center point of a resistor divider between CSREF and CSCOMP is
connected to this pin to set the load line slope.
17 CSREF Current-Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current-sense
amplifier and the power-good and crowbar functions. This pin should be connected to the common point of the
output inductors.
18 CSSUM Current-Sense Summing Node. External resistors from each switch node to this pin sum the inductor currents
together to measure the total output current.
19 CSCOMP Current-Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of the
current-sense amplifier and the positioning loop response time.
20 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
ADP3207
Rev. 1 | Page 9 of 29 | www.onsemi.com
Pin No. Mnemonic Description
21 to 23 SW3 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
24 to 26 PWM3 to
PWM1
Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3419. Connecting the PWM2 and/or PWM3 outputs to VCC causes that phase to turn off, allowing the
ADP3207 to operate as a 1-, 2-, or 3-phase controller.
27
OD
Multiphase Output Disable Logic Output. This pin is actively pulled low when the ADP3207 enters single-phase mode
or during shutdown. Connect this pin to the SD inputs of the Phase-2 and Phase-3 MOSFET drivers.
28
DCM
Discontinuous Current Mode Enable Output. This pin is actively pulled low when the single-phase inductor
current crosses zero.
29 VRTT Voltage Regulator Thermal Throttling Logic Output. This pin goes high if the temperature at the monitoring point
connected to TTSENSE exceeds the programmed VRTT temperature threshold.
30 TTSENSE Thermal Throttling Sense Input and OVP Disable. The center point of a resistor divider (where the lower resistor is
an NTC thermistor) between VCC and GND is connected to this pin to remotely sense the temperature at the
desired thermal monitoring point. Grounding TTSENSE disables OVP function.
31 VCC Supply Voltage for the Device.
32
PSI
Power State Indicator Input. Pulling this pin to GND forces the ADP3207 to operate in single-phase mode.
33
DPRSTP
Deeper Stop Control Input.
34 to 40 VID6 to
VID0
Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB regulation
voltage from 0.3 V to 1.5 V (see Table 6).
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ADP3207JCPZ-RL

Mfr. #:
Buy ADP3207JCPZ-RL
Manufacturer:
ON Semiconductor
Description:
Switching Controllers IMVP6 MLTI/PHSE CNTR
Lifecycle:
New from this manufacturer.
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