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ADP3207JCPZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
ADP3207
Rev. 1 | Page 19 of 29 | www.onsemi.com
APPLICATION INFORMATION
The design parameters for a typical Intel IMVP6-compliant
CPU Core VR application are as follows:
• Maximum input voltage (V
INMAX
) = 19 V
• Minimum input voltage (V
INMIN
) = 7 V
• Output voltage by VID setting (V
VID
) = 1.150 V
• Maximum output current (I
O
) = 44 A
• Load line slope (R
O
) = 2.1 mΩ
• Maximum output current step (ΔI
O
) = 34.5 A
• Maximum output thermal current (I
OTDC
) = 32 A
• Number of phases (n) = 2
• Switching frequency per phase (f
SW
) = 280 kHz
• Duty cycle at maximum input voltage (D
MIN
) = 0.061
• Duty cycle at minimum input voltage (D
MAX
) = 0.164
SETTING THE CLOCK FREQUENCY FOR PWM
MODE
In PWM mode operation, The ADP3207 uses a fixed-frequency
control architecture. The frequency is set by an external timing
resistor (R
T
). The clock frequency and the number of phases
determine the switching frequency per phase, which directly
relates to switching losses, and the sizes of the inductors and
input and output capacitors. In a 2-phase design, a clock
frequency of 560 kHz sets the switching frequency to 280 kHz
per phase. This selection represents a trade-off between the
switching losses and the minimum sizes of the output filter
components. To achieve a 560 kHz oscillator frequency at VID
voltage 1.150 V, R
T
has to be 237 kΩ. Alternatively, the value for
R
T
can be calculated using
Ω−
××
+
= k5
pF16
V0.1
SW
VID
T
fn
V
R
(1)
where 16 pF and 25 kΩ are internal IC component values. For
good initial accuracy and frequency stability, it is recommended
to use a 1% resistor.
SOFT-START AND CURRENT-LIMIT LATCH-OFF
DELAY TIMES
The soft-start and current-limit latch-off delay functions share
the SS pin. Consequently, these two parameters must be
considered together. The first step is to set C
SS
for the soft-start
ramp. This ramp is generated with a 8 µA internal current
source. The value for C
SS
can be set as
BOOT
SS
SS
V
t
C
×
=
μA8
(2)
where:
V
BOOT
is the boot voltage for the CPU, defined in the IMVP-6
specification as 1.2 V.
t
SS
is the desired soft-start time, recommended to be below 3 ms
in the IMVP-6 specification.
Assuming a desired soft-start time of 2 ms, C
SS
is 13.3 nF, with
the closest standard capacitance at 12 nF.
Once C
SS
has been chosen, the current-limit latch-off time is
equal to 7.2 ms according to the following calculation:
μA2
V2.1
SS
DELAY
C
t
×
=
(3)
PWRGD DELAY TIMER
The PWRGD delay, t
CPU_PWRGD
, is defined in the IMVP-6
specification as the time period between the
CLKEN
assertion
and the PWRGD assertion. It is programmed by a cap on the
PGDELAY pin.
V9.2
μA9.1
_ PWRGDCPU
PGDLY
t
C
×
=
(4)
The IMVP-6 specifies that the PWRGD delay is between 3 ms
to 20 ms. Assuming 7 ms PWRGD delay is preferred, then
C
PGDLY
is 4.7 nF.
INDUCTOR SELECTION
The choice of inductance determines the ripple current in the
inductor. Less inductance leads to more ripple current, which
increases the output ripple voltage and conduction losses in the
MOSFETs. However, this allows the use of smaller-size inductors,
and for a specified peak-to-peak transient deviation, it allows
less total output capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses, but
requires larger size inductors and more output capacitance for
the same peak-to-peak transient deviation. In a multiphase
converter, the practical peak-to-peak inductor ripple current is
less than 50% of the maximum dc current in the same inductor.
Equation 5 shows the relationship between the inductance,
oscillator frequency, and peak-to-peak ripple current. Equation
6 can be used to determine the minimum inductance based on
a given output ripple voltage.
(
)
Lf
D
V
I
SW
MINVID
R
×
−×
=
1
(5)
((
))
(
)
RIPPLESW
MINMIN
O
VID
Vf
DDnRV
L
×
−××−××
≥
11
(6)
ADP3207
Rev. 1 | Page 20 of 29 | www.onsemi.com
Solving Equation 6 for a 20 mV peak-to-peak output ripple
voltage yields
(( )
)
()
nH356
mV20kHz280
061.01061.021m1.2V150.1
=
×
−××−×Ω×
≥L
If the ripple voltage ends up being less than the initially selected
value, then the inductor can be changed to a smaller value until
the ripple value is met. This iteration allows optimal transient
response and minimum output decoupling.
The smallest possible inductor should be used to minimize the
number of output capacitors. For this example, choosing a
360 nH inductor is a good starting point, and gives a calculated
ripple current of 10.7 A. The inductor should not saturate at the
peak current of 27.4 A, and should be able to handle the sum of
the power dissipation caused by the average current of 16 A in
the winding and core loss.
Another important factor in the inductor design is the DCR,
which is used to measure phase currents. A large DCR causes
excessive power losses, though too small a value leads to
increased measurement error. This example uses an inductor
with a DCR of 0.89 mΩ.
Selecting a Standard Inductor
Once the inductance and DCR are known, the next step is to
either design an inductor or select a standard inductor that
comes as close as possible to meeting the overall design goals. It
is also important to have the inductance and DCR tolerance
specified to keep the accuracy of the system controlled; 20%
inductance and 15% DCR (at room temperature) are reasonable
assumptions that most manufacturers can meet.
Power Inductor Manufacturers
The following companies provide surface mount power
inductors optimized for high power applications upon request:
• Vishay Dale Electronics, Inc.
http://www.vishay.com
• Panasonic
http://www.panasonic.com
• Sumida Corporation
http://www.sumida.com
• NEC Tokin Corporation
http://www.nec-tokin.com
Output Droop Resistance
The inductor design requires that the regulator output voltage
measured at the CPU pins drops when the output current
increases. The specified voltage drop corresponds to a dc output
resistance (R
O
).
The output current is measured by summing the currents of the
resistors monitoring the voltage across each inductor and by
passing the signal through a low-pass filter. This summer-filter
is implemented by the CS amplifier that is configured with
resistors R
PH(X)
(summer), and R
CS
and C
CS
(filter). The output
resistance of the regulator is set by the following equations,
where R
L
is the DCR of the output inductors:
L
XPH
CS
O
R
R
R
R ×=
)(
(7)
CS
L
CS
RR
L
C
×
=
(8)
Users have the flexibility of choosing either R
CS
or R
PH(X)
. Due to
the current drive ability of the CSCOMP pin, the R
CS
resistance
should be larger than 100 kΩ. For example, users should
initially select R
CS
to be equal to 220 kΩ, then use Equation 8 to
solve for C
CS
nF84.1
k220m89.0
nH360
=
Ω×Ω
=
CS
C
Because C
CS
is not the standard capacitance, it is implemented
with two standard capacitors in parallel: 1.8 nF and 47 pF. For
the best accuracy, C
CS
should be a 5% NPO capacitor.
Next, solve R
PH(X)
by rearranging Equation 7.
Ω=Ω×
Ω
Ω
≥ k2.93k220
m1.2
m89.0
)(XPH
R
The standard 1% resistor for R
PH(X)
is 93.1 kΩ.
Inductor DCR Temperature Correction
With the inductor DCR used as a sense element, and copper
wire being the source of the DCR, users need to compensate for
temperature changes in the inductor’s winding. Fortunately,
copper has a well-known temperature coefficient (TC) of
0.39%/°C.
If R
CS
is designed to have an opposite sign but equal percentage
change in resistance, then it cancels the temperature variation of
the inductor DCR. Due to the nonlinear nature of NTC
thermistors, series resistors, R
CS1
and R
CS2
(see Figure 11) are
needed to linearize the NTC and produce the desired
temperature coefficient tracking.
PLACE AS CLOSE AS POSSIBLE
TO NEAREST INDUCTOR
OR LOW–SIDE MOSFET
KEEP THIS PATH
AS SHORT AS POSSIBLE
AND WELL AWAY FROM
SWITCH NODE LINES
TO
SWITCH
NODES
TO
V
OUT
SENSE
CSREF
CSSUM
CSCOMP
ADP3207
18
17
16
R
PH1
R
TH
R
CS1
C
CS
R
CS2
R
PH2
R
PH3
05782-011
Figure 11. Temperature Compensation Circuit Values
ADP3207
Rev. 1 | Page 21 of 29 | www.onsemi.com
The following procedure and equations yield values for R
CS1
, R
CS2
,
and R
TH
(the thermistor value at 25°C) for a given R
CS
value:
1. Select an NTC to be used based on type and value. Because
there is no value yet, start with a thermistor with a value
close to R
CS
. The NTC should also have an initial tolerance
of better than 5%.
2. Based on the type of NTC, find its relative resistance value
at two temperatures. Temperatures that work well are 50°C
and 90°C. These are called Resistance Value A (A is
R
TH
(50°C)/R
TH
(25°C)) and Resistance Value B (B is
R
TH
(90°C)/R
TH
(25°C)). Note that the relative value of NTC
is always 1 at 25°C.
3. Next, find the relative value of R
CS
that is required for each
of these temperatures. This is based on the percentage of
change needed, which is initially 0.39%/°C. These are
called r
1
and r
2.
()
()
251
1
251
1
2
2
1
1
−×+
=
−×+
=
TTC
r
TTC
r
(9)
where:
TC = 0.0039
T
1
= 50°C
T
2
= 90°C.
4. Compute the relative values for r
CS1
, r
CS2
, and r
TH
using
()
()
()
()
() ( )
()
12
2
1
2
1
21
1221
2
1
1
1
1
1
1
1
11
11
CSCS
TH
CSCS
CS
CS
rr
r
rr
A
r
A
r
BArABrBA
rABrBArrBA
r
−
−
=
−
−
−
−
=
−−×−×−×−×
×−×+×−×−××−
=
(10)
5. Calculate R
TH
= R
TH
×
R
CS
, then select the closest value of
thermistor that is available. Also, compute a scaling factor
k based on the ratio of the actual thermistor value relative
to the computed one
)(
)(
CALCULATEDTH
ACTUALTH
R
R
k =
(11)
6. Finally, calculate values for R
CS1
and R
CS2
using
()
()()
22
11
1
CSCSCS
CSCSCS
rkkRR
rkRR
×+−×=
××=
(12)
This example starts with a thermistor value of 100 kΩ and uses
a Vishay NTHS0603N04 NTC thermistor (a 0603 size thermistor)
with A = 0.3359 and B = 0.0771. From this data, r
CS1
= 0.359,
r
CS2
= 0.729 and r
TH
= 1.094. Solving for R
TH
yields 240 kΩ, so
220 kΩ is chosen, making k = 0.914. Finally, R
CS1
and R
CS2
are
72.3 kΩ and 166 kΩ. Choosing the closest 1% resistor values
yields a choice of 71.5 kΩ and 165 kΩ.
C
OUT
SELECTION
The required output decoupling for processors and platforms is
typically recommended by Intel. The following guidelines can
also be used if both bulk and ceramic capacitors in the system:
• Select the total amount of ceramic capacitance. This is based
on the number and type of capacitors to be used. The best
location for ceramics is inside the socket; 20 pieces of
Size 0805 being the physical limit. Additional capacitors
can be placed along the outer edge of the socket.
• Select the number of ceramics and find the total ceramic
capacitance (C
Z
). Combined ceramic values of 200 µF to
300 µF are recommended and are usually made up of
multiple 10 µF or 22 µF capacitors.
• Note that there is an upper limit imposed on the total
amount of bulk capacitance (C
X
) when considering the
VID on-the-fly output voltage stepping (voltage step V
V
in
time t
V
with error of V
ERR
), and also a lower limit based on
meeting the critical capacitance for load release at a given
maximum load step ΔI
O
. For a step-off load current, the
current version of the IMVP-6 specification allows a
maximum V
CORE
overshoot (V
OSMAX
) of 10 mV, plus 1.5% of
the VID voltage. For example, if the VID is 1.150 V, then
the largest overshoot allowed is 27 mV.
()
¸
¸
¸
¸
¸
¹
·
¨
¨
¨
¨
¨
©
§
−
×
¸
¸
¹
·
¨
¨
©
§
∆
+×
∆×
≥
z
VID
O
OSMAX
O
O
MINx
C
V
I
V
Rn
IL
C
(13)
z
O
V
VID
v
VID
V
2
O
2
MAXX
C
L
nKR
V
V
t
V
V
RnK
L
C −
¸
¸
¸
¹
·
¨
¨
¨
©
§
−
¸
¸
¹
·
¨
¨
©
§
×+××≤ 11
2
)(
(14)
where:
¸
¸
¹
·
¨
¨
©
§
−=
V
ERR
V
V
nK 1
(15)
To meet the conditions of these equations and transient
response, the ESR of the bulk capacitor bank (R
X
) should be less
than two times the droop resistance, R
O
. If the C
X(MIN)
is larger
than C
X(MAX)
, the system does not meet the VID on-the-fly
and/or deeper sleep exit specification and can require a smaller
inductor or more phases (the switching frequency can also have
to be increased to keep the output ripple the same).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

ADP3207JCPZ-RL

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Buy ADP3207JCPZ-RL
Manufacturer:
ON Semiconductor
Description:
Switching Controllers IMVP6 MLTI/PHSE CNTR
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