ADP3207JCPZ-RL Datasheet ADP3207JCPZ-RL | P22-P24

ADP3207

Rev. 1 | Page 22 of 29 | www.onsemi.com

For example, if using 32 pieces of 10 µF 0805 MLC capacitors

= 320 µF), the fastest VID voltage change is the exit of

deeper sleep, and V

CORE

change is 220 mV in 22 µs with a

setting error of 10 mV. Where K = 3.1, solving for the bulk

capacitance yields

()

mF1.1F320

V150.1

A5.34

mV27

m1.22

A5.34nH360

µ−

+Ω×

≥

MINx

()

mF3.2F3201

nH036mV022

m1.21.32V1501.s22

V150.1m1.21.32

mV220nH360

=µ−

−

Ω××××µ

×Ω××

≤

MAXx

Using four 330 µF Panasonic SP capacitors with a typical ESR of

6 mΩ each yields C

= 1.32 mF with an R

= 1.5 mΩ.

One last check should be made to ensure that the ESL of the

bulk capacitors (L

) is low enough to limit the high frequency

ringing during a load change. This is tested using

()

nH22mΩ1.2F320

=××µ≤

××≤

QRCL

(16)

where:

Q is limited to the square root of 2 to ensure a critically damped

system.

In this example, L

is about 250 pH for the four SP capacitors,

which satisfies this limitation. If the L

of the chosen bulk

capacitor bank is too large, the number of ceramic capacitors

may need to be increased if there is excessive ringing.

Note that for this multimode control technique, an all-ceramic

capacitor design can be used as long as the conditions of

Equation 13, Equation 14, and Equation 15 are satisfied.

POWER MOSFETS

For normal 20 A per phase application, the N-channel power

MOSFETs are selected for two high-side switches and two low-

side switches per phase. The main selection parameters for the

power MOSFETs are V

GS(TH)

, Q

, C

ISS

, C

RSS

and R

DS(ON)

. Because

the gate drive voltage (the supply voltage to the ADP3419) is

5 V, logic-level threshold MOSFETs must be used.

The maximum output current I

determines the R

DS(ON)

requirement for the low-side (synchronous) MOSFETs. In the

ADP3207, currents are balanced between phases; the current in

each low-side MOSFET is the output current divided by the

total number of MOSFETs (n

). With conduction losses being

dominant, the following equation shows the total power

dissipated in each synchronous MOSFET in terms of the ripple

current per phase (I

) and average total output current (I

()

)(

SFDS

DP ×

×+

×−=

(17)

Knowing the maximum output thermal current and the

maximum allowed power dissipation, users can find the

required R

DS(ON)

for the MOSFET. For 8-lead SOIC or 8-lead

SOIC compatible packaged MOSFETs, the junction to ambient

(PCB) thermal impedance is 50°C/W. In the worst case, the

PCB temperature is 90°C during heavy load operation of the

notebook; a safe limit for P

is 0.6 W at 120°C junction

temperature. Thus, for this example (32 A maximum thermal

current), R

DS(SF)

(per MOSFET) is less than 9.6 mΩ for two

pieces of low-side MOSFET. This R

DS(SF)

is also at a junction

temperature of about 120°C; therefore, the R

DS(SF)

(per

MOSFET) should be lower than 6.8 mΩ at room temperature,

giving 9.6 mΩ at high temperature.

Another important factor for the synchronous MOSFET is the

input capacitance and feedback capacitance. The ratio of

feedback to input needs to be small (less than 10% is

recommended) to prevent accidental turn-on of the

synchronous MOSFETs when the switch node goes high.

The high-side (main) MOSFET has to be able to handle two

main power dissipation components, conduction and switching

losses. The switching loss is related to the amount of time it

takes for the main MOSFET to turn on and off, and to the

current and voltage that are being switched. Basing the

switching speed on the rise and fall time of the gate driver

impedance and MOSFET input capacitance, Equation 18

provides an approximate value for the switching loss per main

MOSFETs

ISS

OCC

MFS

fP ×××

××= 2

)(

(18)

where:

is the total number of main MOSFETs.

is the total gate resistance (1.5 Ω for the ADP3419 and about

0.5 Ω for two pieces of typical high speed switching MOSFETs,

making R

= 2 Ω).

ISS

is the input capacitance of the main MOSFET. The best

thing to reduce switching loss is to use lower gate capacitance

devices.

The conduction loss of the main MOSFET is given by

)(

MFDS

MFC

DP ×

×+

×=

(19)

where:

DS(MF)

is the on-resistance of the MOSFET.

ADP3207

Rev. 1 | Page 23 of 29 | www.onsemi.com

Typically, for main MOSFETs, users want the highest speed (low

ISS

) device, but these usually have higher on-resistance. Users

must select a device that meets the total power dissipation

(0.6 W for a single 8-lead SOIC package) when combining the

switching and conduction losses.

For example, using an IRF7821 device as the main MOSFET

(four in total; that is, n

= 4), with about C

ISS

= 1010 pF (max)

and R

DS(MF)

= 18 mΩ (max at T

= 120°C) and an IR7832 device

as the synchronous MOSFET (four in total; that is, n

= 4),

DS(SF)

= 6.7 mΩ (max at T

= 120°C). Solving for the power

dissipation per MOSFET at I

= 32 A and I

= 10.7 A yields

420 mW for each synchronous MOSFET and 410 mW for each

main MOSFET.

One last consideration is the power dissipation in the driver for

each phase. This is best described in terms of the QG for the

MOSFETs and is given by the following equation:

()

CCCCGSFSFGMFMF

DRV

VIQnQn

P ×

+×+××

(20)

where:

GMF

is the total gate charge for each main MOSFET.

GSF

is the total gate charge for each synchronous MOSFET.

Also shown is the standby dissipation (I

× V

) of the driver.

For the ADP3419, the maximum dissipation should be less than

300 mW, considering its thermal impedance is 220°C/W and

the maximum temperature increase is 50°C. For this example,

with I

= 2 mA, Q

GMF

= 14 nC and Q

GSF

= 51 nC, there is 120

mW dissipation in each driver, which is below the 300 mW

dissipation limit. See the ADP3419 data sheet for more details.

RAMP RESISTOR SELECTION

The ramp resistor (R

) is used for setting the size of the internal

PWM ramp. The value of this resistor is chosen to provide the

best combination of thermal balance, stability, and transient

response. Use this equation to determine a starting value

Ω=

×Ω××

×××

k282

pF5m4.353

nH3602.0

CRA

(21)

where:

is the internal ramp amplifier gain.

is the current balancing amplifier gain.

is the total low-side MOSFET ON-resistance, C

is the

internal ramp capacitor value.

Another consideration in the selection of R

is the size of the

internal ramp voltage (see Equation 22). For stability and noise

immunity, keep this ramp size larger than 0.5 V. Taking this into

consideration, the value of R

is selected as 280 kΩ.Ҡ

The internal ramp voltage magnitude can be calculated using:

V55.0

kHz280pF5k280

V150.1)061.01(2.0

)1(

××Ω

×−×

××

×−×

SWRR

VIDR

fCR

VDA

(22)

The size of the internal ramp can be made larger or smaller. If it

is made larger, then stability and transient response improves,

but thermal balance degrades. Likewise, if the ramp is made

smaller, then thermal balance improves at the sacrifice of

transient response and stability. The factor of three in the

denominator of Equation 21 sets a minimum ramp size that

gives an optimal balance for good stability, transient response,

and thermal balance.

COMP Pin Ramp

There is a ramp signal on the COMP pin due to the droop

voltage and output voltage ramps. This ramp amplitude adds to

the internal ramp to produce the following overall ramp signal

at the PWM input:

()

×××

×−×

−

OXSW

RCfn

(23)

For this example, the overall ramp signal is found to be 1.5 V.

SETTING THE SWITCHING FREQUENCY FOR RPM

MODE OPERATION OF PHASE 1

During the RPM mode operation of Phase 1, the ADP3207 runs

in pseudo constant frequency, given that the load current is

high enough for continuous current mode. While in

discontinuous current mode, the switching frequency is

reduced with the load current in a linear manner. When

considering power conversion efficiency in light load, lower

switching frequency is usually preferred for RPM mode.

However, the V

CORE

ripple specification in the IMVP-6 sets the

limitation for lowest switching frequency. Therefore, depending

on the inductor and output capacitors, the switching frequency

in RPM mode can be equal, larger, or smaller than its

counterpart in PWM mode.

A resistor between VRPM and RRPM pins sets the pseudo

constant frequency as following:

Ω−

××

×−×

= k5.0

)1(

V0.1

VIDR

VID

RPM

fCR

VDA

(24)

where:

is the internal ramp amplifier gain.

ADP3207

Rev. 1 | Page 24 of 29 | www.onsemi.com

is the internal ramp capacitor value.

is an external resistor on the RAMPADJ pin to set the

internal ramp magnitude.

Because R

= 280 kΩ, the following resistance sets up 300 kHz

switching frequency in RPM operation.

Ωk6.80500

kHz300pF7Ωk280

150.1)061.01(2.0

V0.1V150.1

Ωk2372

=Ω−

××

×−×

RPM

CURRENT-LIMIT SETPOINT

To select the current-limit setpoint, we need to find the resistor

value for R

LIM

. The current-limit threshold for the ADP3207 is

set with a 1.7 V source (V

LIM

) across R

LIM

with a gain of

13 mV/µA. R

LIM

can be found using the following equation:

LIM

LIMLIM

LIM

(25)

For values of R

LIM

greater than 500 kΩ, the current limit may be

lower than expected, so some adjustment of R

LIM

may be

needed. Here, I

LIM

is the average current limit for the output of

the supply. In this example, if choosing 55 A for I

LIM

, R

LIM

190 kΩ, which is close to a standard 1% resistance of 191 kΩ.

The per-phase current limit described earlier has its limit

determined by the following:

)(

MAXDS

BIAS

MAXCOMP

PHLIM

I +

−−

≅

(26)

For the ADP3207, the maximum COMP voltage (V

COMP(MAX)

) is

3.3 V, the COMP pin bias voltage (V

BIAS

) is 1.0 V, and the

current balancing amplifier gain (A

) is 5. Using a V

of 0.55 V,

and a R

DS(MAX)

of 3.8 mΩ (low-side on-resistance at 150°C)

results in a per-phase limit of 85 A. Although this number

seems high, this current level can only be reached with a

absolute short at the output and the current-limit latch-off

function shutting down the regulator before overheating occurs.

This limit can be adjusted by changing the ramp voltage V

However, users should not set the per-phase limit lower than

the average per-phase current (I

LIM

/n).

There is also a per-phase initial duty-cycle limit at maximum

input voltage:

BIAS

MAXCOMP

MINLIM

−

×=

)(

(27)

For this example, the duty-cycle limit at maximum input

voltage is found to be 0.25 when D is 0.061.

FEEDBACK LOOP COMPENSATION DESIGN

Optimized compensation of the ADP3207 allows the best

possible response of the regulator’s output to a load change. The

basis for determining the optimum compensation is to make

the regulator and output decoupling appear as an output

impedance that is entirely resistive over the widest possible

frequency range, including dc, and equal to the droop resistance

). With the resistive output impedance, the output voltage

droops in proportion with the load current at any load current

slew rate. This ensures the optimal positioning and minimizes

the output decoupling.

With the multimode feedback structure of the ADP3207, users

need to set the feedback compensation to make the converter

output impedance work in parallel with the output decoupling.

Several poles and zeros are created by the output inductor and

decoupling capacitors (output filter) that need to be

compensated for.

A type-three compensator on the voltage feedback is adequate

for proper compensation of the output filter. Equation 28 to

Equation 36 is intended to yield an optimal starting point for

the design; some adjustments can be necessary to account for

PCB and component parasitic effects (see the Tuning Procedure

for ADP3207).

The first step is to compute the time constants for all of the

poles and zeros in the system

()

VID

VRCn

DnL

RARnR

×××

××−××

+×+×=

(28)

()

RRCT

−

×+−×=

(29)

(

)

XOXB

CRRR

×−+= '

(30)

EVID

−×

(31)

()

RCRRC

RCC

×+−×

××

(32)

where:

R’ is the PCB resistance from the bulk capacitors to the ceramics.

is the total low-side MOSFET on-resistance per phase.

For this example, A

is 5, V

= 1. 5 V, R’ is approximately

0.4 mΩ (assuming an 8-layer motherboard) and L

is 250 pH

for the four Panasonic SP capacitors.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

ADP3207JCPZ-RL

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Switching Controllers IMVP6 MLTI/PHSE CNTR

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