ADP3207
Rev. 1 | Page 27 of 29 | www.onsemi.com
20. If both overshoots are larger than desired, make the
following adjustments in the order they appear. Note that if
these adjustments do not change the response, then users
are limited by the output decoupling. In addition, check
the output response each time a change is made, as well as
the switching nodes to make sure they are still stable.
a. Make ramp resistor larger by 25% (R
RAMP
).
b. For V
TRAN1
, increase C
B
or increase switching
frequency.
c. For V
TRAN2
, increase R
A
and decrease C
A
both by 25%.
21. For load release (see Figure 16), if V
TRANREL
is larger than
the IMVP-6 specification, there is not enough output
capacitance. Either more capacitance is needed or the
inductor values needed to be smaller. If the inductors are
changed, then start the design over using Equation 1 to
Equation 39 and this tuning guide.
05782-016
V
TRANRE L
V
DROOP
Figure 16. Transient Setting Waveform, Load Release
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
General Recommendations
For effective results, at least a four-layer PCB is recommended.
This allows the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input and output power, and wide interconnection
traces in the rest of the power delivery current paths. Note that
each square unit of 1 ounce copper trace has a resistance of
~0.53 mΩ at room temperature.
When high currents need to be routed between PCB layers, vias
should be used liberally to create several parallel current paths so
that the resistance and inductance introduced by these current
paths are minimized, and the via current rating is not exceeded.
If critical signal lines (including the output voltage sense lines of
the ADP3207) must cross through power circuitry, then a signal
ground plane should be interposed between those signal lines
and the traces of the power circuitry. This serves as a shield to
minimize noise injection into the signals at the expense of
making signal ground a bit noisier.
An analog ground plane should be used around and under the
ADP3207 for referencing the components associated with the
controller. Tie this plane to the nearest output decoupling
capacitor ground. It should not be tied to any other power
circuitry to prevent power currents from flowing in it.
The best location for the ADP3207 is close to the CPU corner
where all the related signal pins are located: VID0 to VID6,
PSI
,
V
CC
SENSE, and V
SS
SENSE.
The components around the ADP3207 should be located close to
the controller with short traces. The most important traces to keep
short and away from other traces are the FB and CSSUM pins (refer
to Figure 10 for more details on layout for the CSSUM node.) The
MLCC for the VCC decoupling should be placed as close to the
VCC pin as possible. In addition, the noise filtering cap on the
TTSENSE pin should also be as close to that pin as possible.
The output capacitors should be connected as closely as possible
to the load (or connector) that receives the power (for example,
a microprocessor core). If the load is distributed, then the
capacitors should also be distributed, and generally in
proportion to where the load tends to be more dynamic.
Power Circuitry
Avoid crossing any signal lines over the switching power path
loop. This path should be routed on the PCB to encompass the
shortest possible length in order to minimize radiated switching
noise energy (that is, EMI) and conduction losses in the board.
Failure to take proper precautions often results in EMI
problems for the entire PC system as well as noise-related
operational problems in the power converter control circuitry.
The switching power path is the loop formed by the current
path through the input capacitors and the power MOSFETs,
including all interconnecting PCB traces and planes. The use of
short and wide interconnection traces is especially critical in this
path for two reasons: it minimizes the inductance in the switching
loop, which can cause high energy ringing, and it accommodates
the high current demand with minimal voltage loss.
