CS5346-CQZ Datasheet CS5346-CQZ, CS5346-CQZR | P1-P3

Preliminary Product Information

This document contains information for a product under development.

Cirrus Logic reserves the right to modify this product without notice.

http://www.cirrus.com

103-dB, 192-kHz, Stereo Audio ADC with 6:1 Input Mux

ADC Features

 Multi-bit Delta–Sigma Modulator

 103 dB Dynamic Range

 -95 dB THD+N

 Stereo 6:1 Input Multiplexer

 Programmable Gain Amplifier (PGA)

– ± 12 dB Gain, 0.5-dB Step Size

– Zero-crossing, Click-free Transitions

 Stereo Microphone Inputs

– +32 dB Gain Stage

– Low-noise Bias Supply

 Up to 192 kHz Sampling Rates

 Selectable 24-bit, Left-justified or I²S Serial

Audio Interface Formats

System Features

 Power-down Mode

 +5 V Analog Power Supply, Nominal

 +3.3 V Digital Power Supply, Nominal

 Direct Interface with 3.3 V to 5 V Logic Levels

 Pin Compatible with CS5345 (*See Section 2

for details.)

General Description

The CS5346 integrates an analog multiplexer, program-

mable gain amplifier, and stereo audio analog-to-digital

converter. The CS5346 performs stereo analog-to-digi-

tal (A/D) conve rsion of 24-bit serial values at sa mple

rates up to 192 kHz.

A 6:1 stereo input multiplexer is included for selecting

between line-level and microphone-level inputs. The

microphone input path includes a +32 dB gain stage

and a low-noise bias voltage supply. The PGA is avail-

able for line or microphone inputs and provides

gain/attenuation of ±12 dB in 0.5 dB steps.

The output of the PGA is followed by an advanced 5th-

order, multi-bit delta-sigma modulator and digital filter-

ing/decimation. Sampled data is transmitted by the

serial audio interface at rates from 8 kHz to 192 kHz in

either Slave or Master Mode.

Integrated level translators allow easy interfacing be-

tween the CS5346 and other devices operating over a

wide range of logic levels.

The CS5346 is available in a 48-pin LQFP package in

Commercial (-40° to +85° C) grade. The CDB5346 Cus-

tomer Demonstration board is also available for device

evaluation and implementation suggestions. Please re-

fer to “Ordering Information” on page 38 for complete

details.

3.3 V to 5 V

Low-Latency

Anti-Alias Filter

Internal Voltage

Reference

Multibit

Oversampling

ADC

Multibit

Oversampling

ADC

Low-Latency

Anti-Alias Filter

High Pass

Filter

High Pass

Filter

Stereo Input 1

Serial

Audio

Output

3.3 V 5 V

MUX

PCM Serial Interface

Level

Translator

Stereo Input 2

Stereo Input 3

Stereo Input 4 /

Mic Input 1 & 2

Stereo Input 5

Stereo Input 6

PGA

+32 dB

Level Translator

Reset

I²C/SPI

Control Data

Interrupt

Overflow

Left PGA Output

Right PGA Output

PGAA

AUG ‘12

DS861PP3

CS5346

2 DS861PP3

CS5346

TABLE OF CONTENTS

1. PIN DESCRIPTIONS - CS5346 ............................................................................................................. 5

2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES ..................................................................... 7

3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8

RECOMMENDED OPERATING CONDITIONS ................................................................................... 8

ABSOLUTE MAXIMUM RATINGS .......................................................................................................8

ANALOG CHARACTERISTICS ............................................................................................................ 9

ANALOG CHARACTERISTICS CONT. .............................................................................................. 10

DIGITAL FILTER CHARACTERISTICS .............................................................................................. 11

DC ELECTRICAL CHARACTERISTICS ............................................................................................. 12

DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 13

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 14

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................ 16

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 17

4. TYPICAL CONNECTION DIAGRAM ................................................................................................... 18

5. APPLICATIONS ................................................................................................................................... 19

5.1 Recommended Power-Up Sequence ............................................................................................. 19

5.2 System Clocking ............................................................................................................................. 19

5.2.1 Master Clock ......................................................................................................................... 19

5.2.2 Master Mode ......................................................................................................................... 20

5.2.3 Slave Mode ........................................................................................................................... 20

5.3 High-Pass Filter and DC Offset Calibration .................................................................................... 20

5.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................21

5.5 Input Connections ........................................................................................................................... 21

5.5.1 Analog Input Configuration for 1 VRMS Input Levels ............................................................ 21

5.5.2 Analog Input Configuration for 2 VRMS Input Levels ............................................................ 22

5.6 PGA Auxiliary Analog Output ......................................................................................................... 23

5.7 Control Port Description and Timing ............................................................................................... 23

5.7.1 SPI Mode ............................................................................................................................... 23

5.7.2 I²C Mode ................................................................................................................................ 24

5.8 Interrupts and Overflow .................................................................................................................. 25

5.9 Reset .............................................................................................................................................. 26

5.10 Synchronization of Multiple Devices ............................................................................................. 26

5.11 Grounding and Power Supply Decoupling .................................................................................... 26

6. REGISTER QUICK REFERENCE ........................................................................................................ 27

7. REGISTER DESCRIPTION .................................................................................................................. 28

7.1 Chip ID - Register 01h .................................................................................................................... 28

7.2 Power Control - Address 02h ......................................................................................................... 28

7.2.1 Freeze (Bit 7) ......................................................................................................................... 28

7.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 28

7.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 28

7.2.4 Power-Down Device (Bit 0) ................................................................................................... 28

7.3 ADC Control - Address 04h ............................................................................................................ 29

7.3.1 Functional Mode (Bits 7:6) .................................................................................................... 29

7.3.2 Digital Interface Format (Bit 4) .............................................................................................. 29

7.3.3 Mute (Bit 2) ............................................................................................................................ 29

7.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 29

7.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 29

7.4 MCLK Frequency - Address 05h .................................................................................................... 30

7.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 30

7.5 PGAOut Control - Address 06h ...................................................................................................... 30

7.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 30

7.6 Channel B PGA Control - Address 07h .......................................................................................

... 30

DS861PP3 3

CS5346

7.6.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 30

7.7 Channel A PGA Control - Address 08h .......................................................................................... 31

7.7.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 31

7.8 ADC Input Control - Address 09h ................................................................................................... 31

7.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 31

7.8.2 Analog Input Selection (Bits 2:0) ........................................................................................... 32

7.9 Active Level Control - Address 0Ch ................................................................................................ 32

7.9.1 Active High/ Low (Bit 0) ......................................................................................................... 32

7.10 Status - Address 0Dh ................................................................................................................... 32

7.10.1 Clock Error (Bit 3) ................................................................................................................ 33

7.10.2 Overflow (Bit 1) .................................................................................................................... 33

7.10.3 Underflow (Bit 0) .................................................................................................................. 33

7.11 Status Mask - Address 0Eh .......................................................................................................... 33

7.12 Status Mode MSB - Address 0Fh ................................................................................................. 33

7.13 Status Mode LSB - Address 10h .................................................................................................. 33

8. PARAMETER DEFINITIONS ................................................................................................................ 34

9. FILTER PLOTS .................................................................................................................................. 35

10. PACKAGE DIMENSIONS .................................................................................................................. 37

11. THERMAL CHARACTERISTICS AND SPECIFICATIONS .............................................................. 37

12. ORDERING INFORMATION ......................................................................................................... 38

13. REVISION HISTORY .......................................................................................................................... 38

LIST OF FIGURES

Figure 1.Master Mode Serial Audio Port Timing ....................................................................................... 15

Figure 2.Slave Mode Serial Audio Port Timing ......................................................................................... 15

Figure 3.Format 0, 24-Bit Data Left-Justified ............................................................................................ 15

Figure 4.Format 1, 24-Bit Data I²S ............................................................................................................ 15

Figure 5.Control Port Timing - I²C Format ................................................................................................. 16

Figure 6.Control Port Timing - SPI Format ................................................................................................ 17

Figure 7.Typical Connection Diagram ....................................................................................................... 18

Figure 8.Master Mode Clocking ................................................................................................................ 20

Figure 9.Analog Input Architecture ............................................................................................................ 21

Figure 10.CS5346 PGA ............................................................................................................................ 22

Figure 11.1 V

RMS

Input Circuit .................................................................................................................. 22

Figure 12.1 V

RMS

Input Circuit with RF Filtering ....................................................................................... 22

Figure 13.2 V

RMS

Input Circuit .................................................................................................................. 22

Figure 14.Control Port Timing in SPI Mode .............................................................................................. 24

Figure 15.Control Port Timing, I²C Write ................................................................................................... 24

Figure 16.Control Port Timing, I²C Read ................................................................................................... 25

Figure 17.Single-Speed Stopband Rejection ............................................................................................ 35

Figure 18.Single-Speed Stopband Rejection ............................................................................................ 35

Figure 19.Single-Speed Transition Band (Detail) ...................................................................................... 35

Figure 20.Single-Speed Passband Ripple ................................................................................................ 35

Figure 21.Double-Speed Stopband Rejection ........................................................................................... 35

Figure 22.Double-Speed Stopband Rejection ........................................................................................... 35

Figure 23.Double-Speed Transition Band (Detail) .................................................................................... 36

Figure 24.Double-Speed Passband Ripple ............................................................................................... 36

Figure 25.Quad-Speed Stopband Rejection ............................................................................................. 36

Figure 26.Quad-Speed Stopband Rejection ............................................................................................. 36

Figure 27.Quad-Speed Transition Band (Detail) ....................................................................................... 36

Figure 28.Quad-Speed Passband Ripple ................................................................................................. 36

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CS5346-CQZ

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Manufacturer:

Cirrus Logic

Description:

Audio A/D Converter ICs 103dB, 24Bit, 192kHz Stereo Audio ADC

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New from this manufacturer.

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CS5346-CQZ

CS5346-CQZ

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