CS5346-CQZ Datasheet CS5346-CQZ, CS5346-CQZR | P31-P33

DS861PP3 31

CS5346

7.7 Channel A PGA Control - Address 08h

7.7.1 Channel A PGA Gain (Bits 5:0)

Function:

Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to

+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.

ample settings.

7.8 ADC Input Control - Address 09h

7.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3)

Function:

Soft Ramp Enable

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-

ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.

See Table 11.

Zero Cross Enable

Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur

on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-

out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal

does not encounter a zero crossing. The zero cross function is independently monitored and implemented

for each channel. See Table 11.

Soft Ramp and Zero Cross Enable

Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or mut-

ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will

occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-

ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-

itored and implemented for each channel. See Table 11.

76543210

Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0

Gain[5:0] Setting

101000 -12 dB

000000 0 dB

011000 +12 dB

Table 10. Example Gain and Attenuation Settings

76543210

Reserved Reserved Reserved PGASoft PGAZero Sel2 Sel1 Sel0

32 DS861PP3

CS5346

7.8.2 Analog Input Selection (Bits 2:0)

Function:

These bits are used to select the input source for the PGA and ADC. Please see Table 12.

7.9 Active Level Control - Address 0Ch

7.9.1 Active High/ Low

(Bit 0)

Function:

When this bit is set, the INT pin functions as an active high CMOS driver.

When this bit is cleared, the INT pin functions as an active low open drain driver and will require an exter-

nal pull-up resistor for proper operation.

7.10 Status - Address 0Dh

For all bits in this register, a ‘1’ means the associated condition has occurred at least once since the register

was last read. A ‘0’ means the associated condition has NOT occurred since the last reading of the register.

Status bits that are masked off in the associated mask register will always be ‘0’ in this register. This register

defaults to 00h.

PGASoft PGAZeroCross Mode

0 0 Changes to affect immediately

0 1 Zero Cross enabled

1 0 Soft Ramp enabled

1 1 Soft Ramp and Zero Cross enabled (default)

Table 11. PGA Soft Cross or Zero Cross Mode Selection

Sel2 Sel1 Sel0 PGA/ADC Input

0 0 0 Microphone-Level Inputs (+32 dB Gain Enabled)

0 0 1 Line-Level Input Pair 1

0 1 0 Line-Level Input Pair 2

0 1 1 Line-Level Input Pair 3

1 0 0 Line-Level Input Pair 4

1 0 1 Line-Level Input Pair 5

1 1 0 Line-Level Input Pair 6

1 1 1 Reserved

Table 12. Analog Input Multiplexer Selection

76543210

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Active_H/L

76543210

Reserved Reserved Reserved Reserved ClkErr Reserved Ovfl Undrfl

DS861PP3 33

CS5346

7.10.1 Clock Error (Bit 3)

Function:

Indicates the occurrence of a clock error condition.

7.10.2 Overflow (Bit 1)

Function:

Indicates the occurrence of an ADC overflow condition.

7.10.3 Underflow (Bit 0)

Function:

Indicates the occurrence of an ADC underflow condition.

7.11 Status Mask - Address 0Eh

Function:

The bits of this register serve as a mask for the Status sources found in the register “Status - Address 0Dh”

on page 32. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status

7.12 Status Mode MSB - Address 0Fh

7.13 Status Mode LSB - Address 10h

Function:

The two Status Mode registers form a 2-bit code for each Status register function. There are three ways to

update the Status register in accordance with the status condition. In the Rising-Edge Active Mode, the sta-

tus bit becomes active on the arrival of the condition. In the Falling-Edge Active Mode, the status bit be-

comes active on the removal of th e condition. In L evel-Active Mode, the status bit is active during the

condition.

00 - Rising edge active

01 - Falling edge active

10 - Level active

11 - Reserved

76543210

Reserved Reserved Reserved Reserved ClkErrM Reserved OvflM UndrflM

76543210

Reserved Reserved Reserved Reserved ClkErr1 Reserved Ovfl1 Undrfl1

Reserved Reserved Reserved Reserved ClkErr0 Reserved Ovfl0 Undrfl0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P38

CS5346-CQZ

Mfr. #:

Buy CS5346-CQZ

Manufacturer:

Cirrus Logic

Description:

Audio A/D Converter ICs 103dB, 24Bit, 192kHz Stereo Audio ADC

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New from this manufacturer.

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CS5346-CQZ

CS5346-CQZ

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