16 DS861PP3
CS5346
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, C
L
=30pF.
13. Data must be held for sufficient time to bridge the transition time, t
fc
, of SCL.
Parameter Symbol Min Max Unit
SCL Clock Frequency f
scl
- 100 kHz
RST
Rising Edge to Start t
irs
500 - ns
Bus Free Time Between Transmissions t
buf
4.7 - µs
Start Condition Hold Time (prior to first clock pulse) t
hdst
4.0 - µs
Clock Low time t
low
4.7 - µs
Clock High Time t
high
4.0 - µs
Setup Time for Repeated Start Condition t
sust
4.7 - µs
SDA Hold Time from SCL Falling (Note 13) t
hdd
0-µs
SDA Setup time to SCL Rising t
sud
250 - ns
Rise Time of SCL and SDA t
rc
, t
rd
-1µs
Fall Time SCL and SDA t
fc
, t
fd
- 300 ns
Setup Time for Stop Condition t
susp
4.7 - µs
Acknowledge Delay from SCL Falling t
ack
300 1000 ns
t
buf
t
hdst
t
low
t
hdd
t
high
t
sud
Stop Start
SDA
SCL
t
irs
RST
t
hdst
t
rc
t
fc
t
sust
t
susp
Start
Stop
Repeated
t
rd
t
fd
t
ack
Figure 5. Control Port Timing - I²C Format
