CS5346-CQZ Datasheet CS5346-CQZ, CS5346-CQZR | P19-P21

DS861PP3 19

CS5346

5. APPLICATIONS

5.1 Recommended Power-Up Sequence

1. Hold RST low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is reset

to its default settings.

2. Bring RST

high. The device will remain in a low power state with the PDN bit set by default. The control

port will be accessible.

3. The desired register settings can be loaded while the PDN bit remains set.

4. Clear the PDN bit to initiate the power-up sequence.

5.2 System Clocking

The CS5346 will operate at sa mpling frequencies from 8 kHz to 200 kHz. This range is div ided into three

speed modes as shown in Table 1.

5.2.1 Master Clock

MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the

frequency at which audio samples for each channel are clocked out of the device. The FM bits (See “Func-

tional Mode (Bits 7:6)” on page 29.) and the MCLK Freq bits (See “MCLK Frequency - Address 05h” on

page 30.) configure the device to generate the proper clocks in Master Mode and receive the proper

clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and

LRCK frequencies.

Mode Sampling Frequency

Single-Speed 8-50 kHz

Double-Speed 50-100 kHz

Quad-Speed 100-200 kHz

Table 1. Speed Modes

LRCK

(kHz)

MCLK (MHz)

* 64x * 96x 128x 192x 256x 384x 512x 768x 1024x

- ---8.1920 12.2880 16.3840 24.5760 32.7680

44.1

- ---11.2896 16.9344 22.5792 33.8680 45.1584

- ---12.2880 18.4320 24.5760 36.8640 49.1520

- - 8.1920 12.2880 16.3840 24.5760 32.7680 - -

88.2

- - 11.2896 16.9344 22.5792 33.8680 45.1584 - -

- - 12.2880 18.4320 24.5760 36.8640 49.1520 - -

128

8.1920 12.2880 16.3840 24.5760 32.7680 - - - -

176.4

11.2896 16.9344 22.5792 33.8680 45.1584 - - - -

192

12.2880 18.4320 24.5760 36.8640 49.1520 - - - -

Mode

QSM

DSM

SSM

* Only available in master mode.

Table 2. Common Clock Frequencies

20 DS861PP3

CS5346

5.2.2 Master Mode

As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from

MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 8.

5.2.3 Slave Mode

In Slave Mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sam-

ple rate, Fs, and must be synchronously derived from the supplied master clock, MCLK.

The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to

128x, 64x or 48x Fs, depending on the desired speed mode. Refer to Table 3 for required clock ratios.

5.3 High-Pass Filter and DC Offset Calibration

When using operational amplifiers in the input circuitry driving the CS5346, a small DC offset may be driven

into the A/D converter. The CS5346 includes a high-pass filter after the decimator to remove any DC offset

which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul-

tichannel system.

The high-pass filter continuously subtracts a measure of the DC offset fro m the output of the decimation

filter. If the HPFFreeze bit (See “High-Pass Filter Freeze (Bit 1)” on page 29.) is set during normal operation,

the current value of the DC offset for the each channel is frozen and this DC offset will continue to be sub-

tracted from the conversion result. This feature makes it possible to perform a system DC offset calibration

by:

1. Running the CS5346 with the high-pass filter enabled until the filter settles. See the Digital Filter Char-

acteristics section for filter settling time.

2. Disabling the high-pass filter and freezing the stored DC offset.

A system calibration performed in this way will eliminate offsets anywhere in the signal path between the

calibration point and the CS5346.

Single-Speed Double-Speed Quad-Speed

SCLK/LRCK Ratio 48x, 64x, 128x 48x, 64x 48x, 64x

Table 3. Slave Mode Serial Bit Clock Ratios

÷256

÷128

÷64

÷4

÷2

÷1

LRCK

SCLK

000

001

010

÷1

÷1.5

÷2

011

100

÷3

÷4

MCLK

FM Bits

MCLK Freq Bits

Figure 8. Master Mode Clocking

DS861PP3 21

CS5346

5.4 Analog Input Multiplexer, PGA, and Mic Gain

The CS5346 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier

(PGA). The input multiplexer can select one of six possible stereo analog input sources and route it to the

PGA. Analog inputs 4A and 4B are able to insert a +32 dB (+40x) gain stage before the input multiplexer,

allowing them to be used for microphone-level signals without the need for any external gain. The PGA

stage provides 12 dB (4x) adjustment in 0.5 dB steps. Figure 9 shows the architecture of the input multi-

plexer, PGA, and microphone gain stages.

The ““Analog Input Selection (Bits 2:0)” on page 32” outlines the bit settings necessary to control the input

multiplexer and mic gain. “Channel B PGA Control - Address 07h” on page 30 and “Channel A PGA Control

- Address 08h” on page 31 outline the register settings necessary to control the PGA. By default, line-

level input 1 is selected, and the PGA is set to 0 dB.

5.5 Input Connections

The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject sig-

nals within the stopband of the filter. However, there is no rejection for input signals which are

 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram

for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capac-

itors which have a lar ge voltage coefficient (such as ge neral-purpose ceramics) must be avoided since

these can degrade signal linearity. Any unused analog input pairs should be left unconnected.

5.5.1 Analog Input Configuration for 1 V

RMS

Input Levels

The CS5346 PGA, excluding the input multiplexer, is shown in Figure 10 with nominal component values.

Interfacing to this circuit is a relatively simple matter and several options are available. The simplest option

is shown in Figure 11. However, it may be advantageous in some applications to provide a low-pass filter

prior to the PGA to prevent radio frequency interference within the amplifier. The circuit shown in Figure 12

MUX

+32 dB

AIN1A

AIN2A

AIN3A

AIN4A/MICIN1

AIN5A

AIN6A

PGA

MUX

+32 dB

AIN1B

AIN2B

AIN3B

AIN4B/MICIN2

AIN5B

AIN6B

Analog Input

Selection Bits

Channel A

PGA Gain Bits

Channel B

PGA Gain Bits

Out to ADC

Channel A

Out to ADC

Channel B

PGA

Figure 9. Analog Input Architecture

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P38

CS5346-CQZ

Mfr. #:

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Manufacturer:

Cirrus Logic

Description:

Audio A/D Converter ICs 103dB, 24Bit, 192kHz Stereo Audio ADC

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CS5346-CQZ

CS5346-CQZ

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