OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MAX6873ETJ+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
MR
The manual reset (MR) input initiates a reset condi-
tion. Register 40h determines the programmable out-
puts that assert while MR is low (Table 6). All affected
programmable outputs remain asserted (see the
Programmable Outputs section) for their PO_ timeout
periods after MR releases high. An internal 10µA cur-
rent source pulls MR to DBP. Leave MR unconnected
or connect to DBP if unused. A programmable output
cannot depend solely on MR.
MARGIN
MARGIN allows system-level testing while power sup-
plies exceed the normal ranges. Registers 41h and
42h determine whether the programmable outputs
assert to a predetermined state or hold the last state
as MARGIN is driven low (Table 7). Drive MARGIN low
to set the programmable outputs in a known state
while system-level testing occurs. Leave MARGIN
unconnected or connect to DBP if unused. An internal
10µA current source pulls MARGIN to DBP. The state
of each programmable output does not change while
MARGIN = GND. MARGIN overrides MR if both assert
at the same time.
Programmable Outputs
The MAX6872 features eight programmable outputs,
while the MAX6873 features five programmable outputs.
Selectable output-stage configurations include: active low
or active high, open drain, weak pullup, push-pull, or
charge pump. During power-up, the programmable out-
puts pull to GND with an internal 10µA current sink for 1V
< V
ABP
< V
UVLO
. The programmable outputs remain in
their active states until their respective PO_ timeout peri-
ods expire, and all of the programmed conditions are met
for each output. Any output programmed to depend on
no condition always remains in its active state (Table 20).
An active-high configured output is considered asserted
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
16 ______________________________________________________________________________________
Table 5. GPI1–GPI4 Active Logic States
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
[0] GPI1. 0 = active low. 1 = active high.
[1] GPI2. 0 = active low. 1 = active high.
[2] GPI3. 0 = active low. 1 = active high.
3Bh 803Bh
[3] GPI4. 0 = active low. 1 = active high.
Table 6. Programmable Output Behavior and MR
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT
RANGE
DESCRIPTION
[0] PO1 (MAX6872 only). 0 = PO1 independent of MR. 1 = PO1 asserts when MR = low.
[1] PO2 (MAX6872 only). 0 = PO2 independent of MR. 1 = PO2 asserts when MR = low.
[2]
PO3 (MAX6872)/PO1 (MAX6873). 0 = PO3/PO1 independent of MR.
1 = PO3/PO1 asserts when MR = low.
[3]
PO4 (MAX6872)/PO2 (MAX6873). 0 = PO4/PO2 independent of MR.
1 = PO4/PO2 asserts when MR = low.
[4]
PO5 (MAX6872)/PO3 (MAX6873). 0 = PO5/PO3 independent of MR.
1 = PO5/PO3 asserts when MR = low.
[5]
PO6 (MAX6872)/PO4 (MAX6873). 0 = PO6/PO4 independent of MR.
1 = PO6/PO4 asserts when MR = low.
[6]
PO7 (MAX6872)/PO5 (MAX6873). 0 = PO7/PO5 independent of MR.
1 = PO7/PO5 asserts when MR = low.
40h 8040h
[7] PO8 (MAX6872 only). 0 = PO8 independent of MR. 1 = PO8 asserts when MR = low.
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
______________________________________________________________________________________ 17
when that output is logic-high. No output can depend
solely on MR.
The positive voltage monitors generate fault signals
(logical 0) to the MAX6872/MAX6873s’ logic array when
an input voltage is below the programmed undervolt-
age threshold, or when that voltage is above the over-
voltage threshold. The negative voltage monitor (IN2)
generates a fault signal to the logic array when the
input voltage is less negative than the undervoltage
threshold, or when that voltage is more negative than
the overvoltage threshold.
Registers 0Eh through 3Ah and 40h configure each of
the programmable outputs. Programmable timing
blocks set the PO_ timeout period from 25µs to 1600ms
Table 7. Programmable Output Behavior and MARGIN
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT
RANGE
AFFECTED OUTPUT DESCRIPTION
[0]
PO1
(MAX6872 only)
0 = output held in existing state.
1 = output asserts high or low (see 42h[0]).
[1]
PO2
(MAX6872 only)
0 = output held in existing state.
1 = output asserts high or low (see 42h[1]).
[2]
PO3 (MAX6872)
PO1 (MAX6873)
0 = output held in existing state.
1 = output asserts high or low (see 42h[2]).
[3]
PO4 (MAX6872)
PO2 (MAX6873)
0 = output held in existing state.
1 = output asserts high or low (see 42h[3]).
[4]
PO5 (MAX6872)
PO3 (MAX6873)
0 = output held in existing state.
1 = output asserts high or low (see 42h[4]).
[5]
PO6 (MAX6872)
PO4 (MAX6873)
0 = output held in existing state.
1 = output asserts high or low (see 42h[5]).
[6]
PO7 (MAX6872)
PO5 (MAX6873)
0 = output held in existing state.
1 = output asserts high or low (see 42h[6]).
41h 8041h
[7]
PO8
(MAX6872 only)
0 = output held in existing state.
1 = output asserts high or low (see 42h[7]).
[0]
PO1
(MAX6872 only)
0 = output asserts low if 41h[0] = 1.
1 = output asserts high if 41h[0] = 1.
[1]
PO2
(MAX6872 only)
0 = output asserts low if 41h[1] = 1.
1 = output asserts high if 41h[1] = 1.
[2]
PO3 (MAX6872)
PO1 (MAX6873)
0 = output asserts low if 41h[2] = 1.
1 = output asserts high if 41h[2] = 1.
[3]
PO4 (MAX6872)
PO2 (MAX6873)
0 = output asserts low if 41h[3] = 1.
1 = output asserts high if 41h[3] = 1.
[4]
PO5 (MAX6872)
PO3 (MAX6873)
0 = output asserts low if 41h[4] = 1.
1 = output asserts high if 41h[4] = 1.
[5]
PO6 (MAX6872)
PO4 (MAX6873)
0 = output asserts low if 41h[5] = 1.
1 = output asserts high if 41h[5] = 1.
[6]
PO7 (MAX6872)
PO5 (MAX6873)
0 = output asserts low if 41h[6] = 1.
1 = output asserts high if 41h[6] = 1.
42h 8042h
[7]
PO8
(MAX6872 only)
0 = output asserts low if 41h[7] = 1.
1 = output asserts high if 41h[7] = 1.
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
18 ______________________________________________________________________________________
Table 8. PO1 (MAX6872 Only) Output Dependency
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT OUTPUT ASSERTION CONDITIONS
[0] 1 = PO1 assertion depends on IN1 primary undervoltage threshold (Table 2).
[1] 1 = PO1 assertion depends on IN2 primary undervoltage threshold (Table 3).
[2] 1 = PO1 assertion depends on IN3 primary undervoltage threshold (Table 4).
[3] 1 = PO1 assertion depends on IN4 primary undervoltage threshold (Table 4).
[4] 1 = PO1 assertion depends on IN5 primary undervoltage threshold (Table 4).
[5] 1 = PO1 assertion depends on IN6 primary undervoltage threshold (Table 4).
[6] 1 = PO1 assertion depends on watchdog 1 (Tables 25 and 26).
0Eh 800Eh
[7] 1 = PO1 assertion depends on watchdog 2 (Tables 25 and 26).
[0] 1 = P O1 asser ti on d ep end s on IN 1 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 2) .
[1] 1 = P O1 asser ti on d ep end s on IN 2 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 3) .
[2] 1 = P O1 asser ti on d ep end s on IN 3 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[3] 1 = P O1 asser ti on d ep end s on IN 4 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[4] 1 = P O1 asser ti on d ep end s on IN 5 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[5] 1 = P O1 asser ti on d ep end s on IN 6 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[6] 1 = PO1 assertion depends on GPI1 (Table 5).
0Fh 800Fh
[7] 1 = PO1 assertion depends on GPI2 (Table 5).
[0] 1 = PO1 assertion depends on GPI3 (Table 5).
[1] 1 = PO1 assertion depends on GPI4 (Table 5).
[2] 1 = PO1 assertion depends on PO2 (Table 9).
[3] 1 = PO1 assertion depends on PO3 (Tables 10 and 11).
[4] 1 = PO1 assertion depends on PO4 (Tables 12 and 13).
[5] 1 = PO1 assertion depends on PO5 (Tables 14 and 15).
[6] 1 = PO1 assertion depends on PO6 (Tables 16 and 17).
10h 8010h
[7] 1 = PO1 assertion depends on PO7 (Table 18).
11h 8011h [0] 1 = PO1 assertion depends on PO8 (Table 19).
40h 8040h [0] 1 = PO1 asserts when MR = low (Table 6).
for each programmable output. See register 3Ah (Table
20) to set the active state (active-high or active-low) for
each programmable output and registers 11h, 15h,
1Ch, 23h, 2Ah, 31h, 35h, and 39h to select the output
stage types (Tables 21 and 22), and PO_ timeout peri-
ods (Table 23) for each output.
Control selected programmable outputs with a sum of
products (Tables 8–19). Each product allows a different
set of conditions to assert each output. Outputs PO3
(MAX6872)/PO1 (MAX6873) and PO6 (MAX6872)/
PO4 (MAX6873) allow two sets of different conditions to
assert each output. Outputs PO1 and PO2 (MAX6872
only), PO7 (MAX6872)/PO5 (MAX6873), and PO8
(MAX6872 only) allow only one set of conditions to
assert each output.
For example, Product 1 of the PO3 (MAX6872—Table
10) programmable output may depend on the IN1 pri-
mary undervoltage threshold, and the states of GPI1,
PO1, and PO2. Write a one to R16h[0], R17h[6], and
R18h[3:2] to configure Product 1 as indicated. IN1
must be above the primary undervoltage threshold
(Table 2), GPI1 must be inactive (Table 5), and PO1
(Tables 8 and 20) and PO2 (Tables 10 and 21) must
be in their deasserted states for Product 1 to be a logi-
cal 1. Product 1 is equivalent to the logic statement:
V1A • GPI1 • PO1 • PO2.
Product 2 of PO3 (MAX6872, Table 11) may depend on
an entirely different set of conditions, or the same condi-
tions, depending on the system requirements. For
example, Product 2 may depend on the IN1 undervolt-
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

MAX6873ETJ+

Mfr. #:
Buy MAX6873ETJ+
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits EEPROM-Prog Quad Power-Sup Sequencer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet