2 5 PO3
Programmable Output 3. Configurable, active-high, active-low, open-drain, weak pullup
(MAX6872), push-pull (MAX6873), or charge-pump (MAX6872) output. PO3 pulls low with
a 10µA internal current sink for 1V < V
ABP
< V
UVLO
. PO3 assumes its programmed
conditional output state when ABP exceeds UVLO.
3 6 PO4
Programmable Output 4. Configurable, active-high, active-low, open-drain, weak pullup
(MAX6872), push-pull (MAX6873), or charge-pump (MAX6872) output. PO4 pulls low with
a 10µA internal current sink for 1V < V
ABP
< V
UVLO
. PO4 assumes its programmed
conditional output state when ABP exceeds UVLO.
4 4 GND Ground
5 7 PO5
Programmable Output 5. Configurable, active-high, active-low, open-drain, weak pullup, or
push-pull output. PO5 pulls low with a 10µA internal current sink for 1V < V
ABP
< V
UVLO
.
PO5 assumes its programmed conditional output state when ABP exceeds UVLO.
6 — PO6
Programmable Output 6. Configurable, active-high, active-low, open-drain, weak pullup, or
push-pull output. PO6 pulls low with a 10µA internal current sink for 1V < V
ABP
< V
UVLO
.
PO6 assumes its programmed conditional output state when ABP exceeds UVLO.
7 — PO7
Programmable Output 7. Configurable, active-high, active-low, open-drain, weak pullup, or
push-pull output. PO7 pulls low with a 10µA internal current sink for 1V < V
ABP
< V
UVLO
.
PO7 assumes its programmed conditional output state when ABP exceeds UVLO.
8 — PO8
Programmable Output 8. Configurable, active-high, active-low, open-drain, weak pullup, or
push-pull output. PO8 pulls low with a 10µA internal current sink for 1V < V
ABP
< V
UVLO
.
PO8 assumes its programmed conditional output state when ABP exceeds UVLO.
9, 10, 23,
24
1, 8, 9, 10,
Margin Input. Configure MARGIN to either assert PO_ into a programmed state or to hold
PO_ in its existing state when driving MARGIN low (see Table 7). Leave MARGIN
unconnected or connect to DBP if unused. MARGIN overrides MR if both assert at the
same time. MARGIN is internally pulled up to DBP through a 10µA current source.
12 12 MR
Manual Reset Input. Configure MR to either assert PO_ into a programmed state or to have
no effect on PO_ when driving MR low (see Table 6). Leave MR unconnected or connect
to DBP if unused. MR is internally pulled up to DBP through a 10µA current source.
13 13 SDA Serial Data Input/Output (Open-Drain). SDA requires an external pullup resistor.
14 14 SCL Serial Clock Input. SCL requires an external pullup resistor.
15 15 A0
Address Input 0. Address inputs allow up to four MAX6872/MAX6873 connections on one
common bus. Connect A0 to GND or to the serial interface power supply.
16 16 A1
Address Input 1. Address inputs allow up to four MAX6872/MAX6873 connections on one
common bus. Connect A1 to GND or to the serial interface power supply.
