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MAX6873ETJ+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
______________________________________________________________________________________ 19
age threshold, and the states of GPI2 and WD1. Write
ones to R19h[6, 0] and R1Ah[7] to configure Product 2
as indicated. IN1 must be above the primary undervolt-
age threshold (Table 2), GPI2 must be inactive (Table
5), and the WD1 timer must not have expired (Tables 25
and 26) for Product 2 to be a logical 1. Product 2 is
equivalent to the logic statement: V1A • GPI2 • WD1.
PO3 deasserts if either Product 1 or Product 2 is a logi-
cal 1. The logical statement: Product 1 + Product 2
determines the state of PO3.
Table 8 only applies to PO1 of the MAX6872. Write a 0
to a bit to make the PO1 output independent of the
respective signal (IN1–IN6 primary or secondary
thresholds, WD1 or WD2, GPI1–GPI4, MR, or other pro-
grammable outputs).
Table 9 only applies to PO2 of the MAX6872. Write a 0
to a bit to make the PO2 output independent of the
respective signal (IN1–IN6 primary or secondary
thresholds, WD1 or WD2, GPI1–GPI4, MR, or other pro-
grammable outputs).
Table 9. PO2 (MAX6872 Only) Output Dependency
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT OUTPUT ASSERTION CONDITIONS
[0] 1 = PO2 assertion depends on IN1 primary undervoltage threshold (Table 2).
[1] 1 = PO2 assertion depends on IN2 primary undervoltage threshold (Table 3).
[2] 1 = PO2 assertion depends on IN3 primary undervoltage threshold (Table 4).
[3] 1 = PO2 assertion depends on IN4 primary undervoltage threshold (Table 4).
[4] 1 = PO2 assertion depends on IN5 primary undervoltage threshold (Table 4).
[5] 1 = PO2 assertion depends on IN6 primary undervoltage threshold (Table 4).
[6] 1 = PO2 assertion depends on watchdog 1 (Tables 25 and 26).
12h 8012h
[7] 1 = PO2 assertion depends on watchdog 2 (Tables 25 and 26).
[0] 1 = P O2 asser ti on d ep end s on IN 1 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 2) .
[1] 1 = P O2 asser ti on d ep end s on IN 2 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 3) .
[2] 1 = P O2 asser ti on d ep end s on IN 3 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[3] 1 = P O2 asser ti on d ep end s on IN 4 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[4] 1 = P O2 asser ti on d ep end s on IN 5 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[5] 1 = P O2 asser ti on d ep end s on IN 6 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[6] 1 = PO2 assertion depends on GPI1 (Table 5).
13h 8013h
[7] 1 = PO2 assertion depends on GPI2 (Table 5).
[0] 1 = PO2 assertion depends on GPI3 (Table 5).
[1] 1 = PO2 assertion depends on GPI4 (Table 5).
[2] 1 = PO2 assertion depends on PO1 (Table 8).
[3] 1 = PO2 assertion depends on PO3 (Tables 10 and 11).
[4] 1 = PO2 assertion depends on PO4 (Tables 12 and 13).
[5] 1 = PO2 assertion depends on PO5 (Tables 14 and 15).
[6] 1 = PO2 assertion depends on PO6 (Tables 16 and 17).
14h 8014h
[7] 1 = PO2 assertion depends on PO7 (Table 18).
15h 8015h [0] 1 = PO2 assertion depends on PO8 (Table 19).
40h 8040h [1] 1 = PO2 asserts when MR = low (Table 6).
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
20 ______________________________________________________________________________________
Table 10. PO3 (MAX6872)/PO1 (MAX6873) Output Dependency (Product 1)
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT OUTPUT ASSERTION CONDITIONS
[0] 1 = PO3/PO1 assertion depends on IN1 primary undervoltage threshold (Table 2).
[1] 1 = PO3/PO1 assertion depends on IN2 primary undervoltage threshold (Table 3).
[2] 1 = PO3/PO1 assertion depends on IN3 primary undervoltage threshold (Table 4).
[3] 1 = PO3/PO1 assertion depends on IN4 primary undervoltage threshold (Table 4).
[4]
1 = PO3 (MAX6872 only) assertion depends on IN5 primary undervoltage threshold (Table 4).
Must be set to 0 for the MAX6873.
[5]
1 = PO3 (MAX6872 only) assertion depends on IN6 primary undervoltage threshold (Table 4).
Must be set to 0 for the MAX6873.
[6] 1 = PO3/PO1 assertion depends on watchdog 1 (Tables 25 and 26).
16h 8016h
[7] 1 = PO3/PO1 assertion depends on watchdog 2 (Tables 25 and 26).
[0] 1 = P O3/P O1 asser ti on d ep end s on IN 1 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 2) .
[1] 1 = P O3/P O1 asser ti on d ep end s on IN 2 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 3) .
[2] 1 = P O3/P O1 asser ti on d ep end s on IN 3 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[3] 1 = P O3/P O1 asser ti on d ep end s on IN 4 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[4]
1 = PO3 (MAX6872 only) assertion depends on IN5 secondary undervoltage/overvoltage
threshold (Table 4). Must be set to 0 for the MAX6873.
[5]
1 = PO3 (MAX6872 only) assertion depends on IN6 secondary undervoltage/overvoltage
threshold (Table 4). Must be set to 0 for the MAX6873.
[6] 1 = PO3/PO1 assertion depends on GPI1 (Table 5).
17h 8017h
[7] 1 = PO3/PO1 assertion depends on GPI2 (Table 5).
[0] 1 = PO3/PO1 assertion depends on GPI3 (Table 5).
[1] 1 = PO3/PO1 assertion depends on GPI4 (Table 5).
[2] 1 = P O3 ( M AX 6872 onl y) asser ti on d ep end s on P O1 ( Tab l e 8) . M ust b e set to 0 for the M AX 6873.
[3] 1 = P O3 ( M AX 6872 onl y) asser ti on d ep end s on P O2 ( Tab l e 9) . M ust b e set to 0 for the M AX 6873.
[4] 1 = PO3/PO1 assertion depends on PO4 (MAX6872)/PO2 (MAX6873) (Tables 12 and 13).
[5] 1 = P O3/P O 1 asser ti on d ep end s on P O5 ( M AX 6872) /P O 3 ( M AX 6873) ( Tab l es 14 and 15) .
[6] 1 = PO3/PO1 assertion depends on PO6 (MAX6872)/PO4 (MAX6873) (Tables 16 and 17).
18h 8018h
[7] 1 = PO3/PO1 assertion depends on PO7 (MAX6872)/PO5 (MAX6873) (Table 18).
1Ch 801Ch [0] 1 = P O3 ( M AX 6872 onl y) asser ti on d ep end s on P O8 ( Tab l e 19) . M ust b e set to 0 for the M AX 6873.
40h 8040h [2] 1 = PO3/PO1 asserts when MR = low (Table 6).
Table 10 only applies to PO3 of the MAX6872 and PO1
of the MAX6873. Write a 0 to a bit to make the PO3/PO1
output independent of the respective signal (IN_ primary
or secondary thresholds, WD1 or WD2, GPI1–GPI4, MR,
or other programmable outputs). See Table 11 for
Product 2. PO3 (MAX6872)/PO1 (MAX6873) deasserts
when Product 1 or Product 2 = 1.
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
______________________________________________________________________________________ 21
Table 11 only applies to PO3 of the MAX6872 and PO1
of the MAX6873. Write a 0 to a bit to make the PO3/PO1
output independent of the respective signal (IN_ primary
or secondary thresholds, WD1 or WD2, GPI1–GPI4, MR,
or other programmable outputs). See Table 10 for
Product 1. PO3 (MAX6872)/PO1 (MAX6873) deasserts
when Product 1 or Product 2 = 1.
Table 11. PO3 (MAX6872)/PO1 (MAX6873) Output Dependency (Product 2)
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT OUTPUT ASSERTION CONDITIONS
[0] 1 = PO3/PO1 assertion depends on IN1 primary undervoltage threshold (Table 2).
[1] 1 = PO3/PO1 assertion depends on IN2 primary undervoltage threshold (Table 3).
[2] 1 = PO3/PO1 assertion depends on IN3 primary undervoltage threshold (Table 4).
[3] 1 = PO3/PO1 assertion depends on IN4 primary undervoltage threshold (Table 4).
[4]
1 = PO3 (MAX6872 only) assertion depends on IN5 primary undervoltage threshold (Table 4).
Must be set to 0 for the MAX6873.
[5]
1 = PO3 (MAX6872 only) assertion depends on IN6 primary undervoltage threshold (Table 4).
Must be set to 0 for the MAX6873.
[6] 1 = PO3/PO1 assertion depends on watchdog 1 (Tables 25 and 26).
19h 8019h
[7] 1 = PO3/PO1 assertion depends on watchdog 2 (Tables 25 and 26).
[0] 1 = P O3/P O1 asser ti on d ep end s on IN 1 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 2) .
[1] 1 = P O3/P O1 asser ti on d ep end s on IN 2 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 3) .
[2] 1 = P O3/P O1 asser ti on d ep end s on IN 3 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[3] 1 = P O3/P O1 asser ti on d ep end s on IN 4 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[4]
1 = PO3 (MAX6872 only) assertion depends on IN5 secondary undervoltage/overvoltage
threshold (Table 4). Must be set to 0 for the MAX6873.
[5]
1 = PO3 (MAX6872 only) assertion depends on IN6 secondary undervoltage/overvoltage
threshold (Table 4). Must be set to 0 for the MAX6873.
[6] 1 = PO3/PO1 assertion depends on GPI1 (Table 5).
1Ah 801Ah
[7] 1 = PO3/PO1 assertion depends on GPI2 (Table 5).
[0] 1 = PO3/PO1 assertion depends on GPI3 (Table 5).
[1] 1 = PO3/PO1 assertion depends on GPI4 (Table 5).
[2] 1 = P O3 ( M AX 6872 onl y) asser ti on d ep end s on P O1 ( Tab l e 8) . M ust b e set to 0 for the M AX 6873.
[3] 1 = P O3 ( M AX 6872 onl y) asser ti on d ep end s on P O2 ( Tab l e 9) . M ust b e set to 0 for the M AX 6873.
[4] 1 = P O3/P O 1 asser ti on d ep end s on P O4 ( M AX 6872) /P O 2 ( M AX 6873) ( Tab l es 12 and 13) .
[5] 1 = P O3/P O 1 asser ti on d ep end s on P O5 ( M AX 6872) /P O 3 ( M AX 6873) ( Tab l es 14 and 15) .
[6] 1 = P O3/P O 1 asser ti on d ep end s on P O6 ( M AX 6872) /P O 4 ( M AX 6873) ( Tab l es 16 and 17) .
1Bh 801Bh
[7] 1 = PO3/PO1 assertion depends on PO7 (MAX6872)/PO5 (MAX6873) (Table 18).
1Ch 801Ch [1] 1 = P O3 ( M AX 6872 onl y) asser ti on d ep end s on P O8 ( Tab l e 19) . M ust b e set to 0 for the M AX 6873.
40h 8040h [2] 1 = PO3/PO1 asserts when MR = low (Table 6).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

MAX6873ETJ+

Mfr. #:
Buy MAX6873ETJ+
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits EEPROM-Prog Quad Power-Sup Sequencer
Lifecycle:
New from this manufacturer.
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