MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
______________________________________________________________________________________ 41
programmable outputs) connects to the reset input or a
nonmaskable interrupt of the µP.
Registers 3Ch–3Fh configure the watchdog functionality
of the MAX6872/MAX6873. Program each watchdog
timer to assert one or more programmable outputs (see
Tables 8–19). Program each watchdog timer to reset on
one of the GPI_ inputs, one of the programmable out-
puts, or a combination of one GPI_ input and one pro-
grammable output.
Each watchdog timer features independent initial and
normal watchdog timeout periods. The initial watchdog
timeout period applies immediately after power-up, after a
reset event takes place, or after enabling the watchdog
timer. The initial watchdog timeout period allows the µP to
perform its initialization process. If no pulse occurs during
the initial watchdog timeout period, the µP is taking too
long to initialize, indicating a potential problem.
The normal watchdog timeout period applies in every
other cycle after the initial watchdog timeout period
occurs. The normal watchdog timeout period monitors
a pulsed output of the µP that indicates when normal
processor behavior occurs. If no pulse occurs during
the normal watchdog timeout period, this indicates that
the processor has stopped operating or is stuck in an
infinite execution loop.
Disable or enable each initial timeout period through reg-
isters 3Ch and 3Eh. Registers 3Dh and 3Fh program the
initial and normal watchdog timeout periods, and enable
or disable each watchdog timer. See Tables 25 and 26
for a summary of the watchdog behavior.
Fault Detector
Registers 60h–62h store all fault conditions, including
undervoltage, overvoltage, GPI_, and watchdog timer
faults (see Table 27). Fault registers are read-only and
lose contents upon power removal. The first read com-
mand from the fault registers after power-up gives invalid
data. Any MR assertion writes to the fault register.
Reading the fault register clears all fault flags. Both GPI_
and WD_ bits assert if any of the GPI_ inputs are config-
ured as watchdog inputs (WD_) and a watchdog fault
occurs.
Table 25. Watchdog Inputs (Addresses 3Ch (Watchdog 1), 3Eh (Watchdog 2))
DESCRIPTION
[1:0]
Watchdog Input Selection:
00 = GPI1
01 = GPI2
10 = GPI3
11 = GPI4
[4:2]
Watchdog Internal Input Selection:
000 = PO1 (MAX6872), not used (MAX6873)
001 = PO2 (MAX6872), not used (MAX6873)
010 = PO3 (MAX6872), PO1 (MAX6873)
011 = PO4 (MAX6872), PO2 (MAX6873)
100 = PO5 (MAX6872), PO3 (MAX6873)
101 = PO6 (MAX6872), PO4 (MAX6873)
110 = PO7 (MAX6872), PO5 (MAX6873)
111 = PO8 (MAX6872), not used (MAX6873)
[6:5]
Watchdog Dependency on Inputs:
00 = 11 = Watchdog clear depends on both GPI_ from 3Ch[1:0]
(watchdog 1) or 3Eh[1:0] (watchdog 2) and PO_ from 3Ch[4:2]
(watchdog 1) or 3Eh[4:2] (watchdog 2).
01 = watchdog clear depends only on PO_ from 3Ch[4:2] (watchdog 1)
or 3Eh[4:2] (watchdog 2).
10 = watchdog clear depends only on GPI_ from 3Ch[1:0] (watchdog 1)
or 3Eh[1:0] (watchdog 2).
