MAX6873ETJ+ Datasheet MAX6873ETJ+, MAX6872ETJ+T, MAX6873ETJ+T | P31-P33

MAX6872/MAX6873

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

______________________________________________________________________________________ 31

Charge-Pump Output Configuration

Configure the programmable outputs of the MAX6872/

MAX6873 as charge-pump outputs to drive n-channel

FETs for power-supply sequencing applications. Only

PO1–PO4 (MAX6872) or PO1 and PO2 (MAX6873) can be

configured as charge-pump output stages. The

charge-pump output high voltage is typically V

ABP

+5.5V when unloaded.

Push-Pull Output Configuration

The MAX6872/MAX6873s’ programmable outputs sink

4mA and source 10mA when configured as push-pull

outputs. Only PO5–PO8 (MAX6872) or PO3–PO5

(MAX6873) can be configured as push-pull output

stages. The push-pull output stages refer to any of

IN3–IN6 (MAX6872)/IN3–IN4 (MAX6873) as configured

in Tables 21 and 22. Use the push-pull output configu-

ration to drive loads with fast rise/fall times, or those

with low impedance.

Weak Pullup Output Configuration

The MAX6872/MAX6873s’ programmable outputs sink

4mA when configured as weak pullups. The weak pullup

of 10kΩ refers to any of IN3–IN6 (MAX6872)/IN3–IN4

(MAX6873) or ABP as configured in Tables 21 and 22.

All programmable outputs of the MAX6872/MAX6873

may be configured as weak pullups.

Open-Drain Output Configuration

Connect an external pullup resistor from the program-

mable output to an external voltage when configured as

an open-drain output. PO1–PO4 (PO1 and PO2 for the

MAX6873) may be pulled up to +13.2V. PO5–PO8

(PO3–PO5 for the MAX6873) may be pulled up to a

voltage less than or equal to ABP. Choose the pullup

resistor depending on the number of devices connect-

ed to the open-drain output and the allowable current

consumption. The open-drain output configuration

allows wire-ORed connections, and provides flexibility

in setting the pullup current.

Configuring the MAX6872/MAX6873

The MAX6872/MAX6873 factory-default configuration

sets all EEPROM registers to 00h except register 3Ah,

which is set to FFh. This configuration sets all of the pro-

grammable outputs as active high, open drain (putting

all outputs into high-impedance states until the device is

reconfigured by the user). Each device requires configu-

ration before full power is applied to the system. To con-

figure the MAX6872/MAX6873, first apply an input

voltage to IN1 or one of IN3–IN6 (MAX6872)/IN3–IN4

(MAX6873) (see the Powering the MAX6872/MAX6873

section). V

IN1

> +4V or one of V

IN3

–V

IN6

> +2.7V, to

ensure device operation. Next, transmit data through the

serial interface. Use the block write protocol to quickly

configure the device. Write to the configuration registers

first to ensure the device is configured properly. After

completing the setup procedure, use the read word pro-

tocol to verify the data from the configuration registers.

Lastly, use the write word protocol to write this data to

the EEPROM registers. After completing EEPROM regis-

ter configuration, apply full power to the system to begin

normal operation. The non-volatile EEPROM stores the

latest configuration upon removal of power. Write zeros

to all EEPROM registers to clear the memory.

Software Reboot

A software reboot allows the user to restore the

EEPROM configuration to the volatile registers without

cycling the power supplies. Use the send byte com-

mand with data byte 88h to initiate a software reboot.

The 3.5ms (max) power-up delay also applies after a

software reboot.

Table 23. PO_ Timeout Periods

AFFECTED OUTPUTS

ADDRESS

EEPROM

MEMORY

ADDRESS

BIT RANGE

MAX6872 MAX6873

DESCRIPTION

11h 8011h [3:1] PO1 —

15h 8015h [3:1] PO2 —

1Ch 801Ch [4:2] PO3 PO1

23h 8023h [4:2] PO4 PO2

2Ah 802Ah [3:1] PO5 PO3

31h 8031h [3:1] PO6 PO4

35h 8035h [3:1] PO7 PO5

39h 8039h [3:1] PO8 —

000 = 25µs

001 = 1.5625ms

010 = 6.25ms

011 = 25ms

100 = 50ms

101 = 200ms

110 = 400ms

111 = 1600ms

MAX6872/MAX6873

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

32 ______________________________________________________________________________________

STOP

CONDITION

REPEATED START

CONDITION

START

CONDITION

HIGH

LOW

SU:DAT

SU:STA

SU:STO

HD:STA

BUF

HD:STA

HD:DAT

SCL

SDA

START

CONDITION

Figure 2. Serial-Interface Timing Details

DATA LINE STABLE,

DATA VALID

SDA

SCL

CHANGE OF

DATA ALLOWED

Figure 3. Bit Transfer

START

CONDITION

SDA

SCL

STOP

CONDITION

Figure 4. Start and Stop Conditions

SMBus/I

C-Compatible Serial Interface

The MAX6872/MAX6873 feature an I

C/SMBus-compati-

ble serial interface consisting of a serial data line (SDA)

and a serial clock line (SCL). SDA and SCL allow bidirec-

tional communication between the MAX6872/MAX6873

and the master device at clock rates up to 400kHz. Figure

2 shows the interface timing diagram. The

MAX6872/MAX6873 are transmit/receive slave-only

devices, relying upon a master device to generate a

clock signal. The master device (typically a microcon-

troller) initiates data transfer on the bus and generates

SCL to permit that transfer.

A master device communicates to the MAX6872/

MAX6873 by transmitting the proper address followed by

command and/or data words. Each transmit sequence is

framed by a START (S) or REPEATED START (SR) condi-

tion and a STOP (P) condition. Each word transmitted

over the bus is 8 bits long and is always followed by an

acknowledge pulse.

SCL is a logic input, while SDA is a logic input/open-

drain output. SCL and SDA both require external pullup

resistors to generate the logic-high voltage. Use 4.7kΩ

for most applications.

Bit Transfer

Each clock pulse transfers one data bit. The data on

SDA must remain stable while SCL is high (Figure 3),

otherwise the MAX6872/MAX6873 register a START or

STOP condition (Figure 4) from the master. SDA and

SCL idle high when the bus is not busy.

MAX6872/MAX6873

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

______________________________________________________________________________________ 33

Start and Stop Conditions

Both SCL and SDA idle high when the bus is not busy. A

master device signals the beginning of a transmission

with a START (S) condition (Figure 4) by transitioning

SDA from high to low while SCL is high. The master

device issues a STOP (P) condition (Figure 4) by transi-

tioning SDA from low to high while SCL is high. A STOP

condition frees the bus for another transmission. The bus

remains active if a REPEATED START condition is gener-

ated, such as in the block read protocol (see Figure 7).

Early STOP Conditions

The MAX6872/MAX6873 recognize a STOP condition at

any point during transmission except if a STOP condition

occurs in the same high pulse as a START condition. This

condition is not a legal I

C format. At least one clock

pulse must separate any START and STOP conditions.

Repeated START Conditions

A REPEATED START (SR) condition may indicate a

change of data direction on the bus. Such a change

occurs when a command word is required to initiate a

read operation (see Figure 7). SR may also be used

when the bus master is writing to several I

C devices

and does not want to relinquish control of the bus. The

MAX6872/MAX6873 serial interface supports continu-

ous write operations with or without an SR condition

separating them. Continuous read operations require

SR conditions because of the change in direction of

data flow.

Acknowledge

The acknowledge bit (ACK) is the 9th bit attached to any

8-bit data word. The receiving device always generates

an ACK. The MAX6872/MAX6873 generate an ACK

when receiving an address or data by pulling SDA low

during the 9th clock period (Figure 5). When transmitting

data, such as when the master device reads data back

from the MAX6872/MAX6873, the MAX6872/MAX6873

wait for the master device to generate an ACK.

Monitoring ACK allows for detection of unsuccessful data

transfers. An unsuccessful data transfer occurs if the

receiving device is busy or if a system fault has

occurred. In the event of an unsuccessful data transfer,

the bus master should reattempt communication at a

later time. The MAX6872/MAX6873 generate a NACK

after the slave address during a software reboot, while

writing to the EEPROM, or when receiving an illegal

memory address.

Slave Address

The MAX6872/MAX6873 slave address conforms to the

following table:

SCL

SDA BY

TRANSMITTER

SDA BY

RECEIVER

START

CONDITION

CLOCK PULSE FOR ACKNOWLEDGE

Figure 5. Acknowledge

X = Don’t care.

SA7

(MSB)

SA6 SA5 SA4 SA3 SA2 SA1

SA0

(LSB)

1 010

A1 A0

R/W

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48

MAX6873ETJ+

Mfr. #:

Buy MAX6873ETJ+

Manufacturer:

Maxim Integrated

Description:

Supervisory Circuits EEPROM-Prog Quad Power-Sup Sequencer

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX6873ETJ+

MAX6873ETJ+

Products related to this Datasheet