MAX6872/MAX6873
Detailed Description
The MAX6872/MAX6873 EEPROM-configurable, multi-
voltage supply sequencers/supervisors monitor several
voltage-detector inputs and four general-purpose logic
inputs, and feature programmable outputs for highly
configurable, power-supply sequencing applications.
The MAX6872 features six voltage-detector inputs and
eight programmable outputs, while the MAX6873 fea-
tures four voltage-detector inputs and five programma-
ble outputs. Manual reset and margin disable inputs
simplify board-level testing during the manufacturing
process. The MAX6872/MAX6873 feature an accurate
internal 1.25V reference.
All voltage detectors provide two configurable thresh-
olds for undervoltage/overvoltage or dual undervoltage
detection. One high-voltage input (IN1) provides detec-
tor threshold voltages from +1.25V to +7.625V in 25mV
increments or +2.5V to +13.2V in 50mV increments.
A bipolar input (IN2) provides detector threshold volt-
ages from ±1.25V to ±7.625V in 25mV increments, or
±2.5V to ±15.25V in 50mV increments. Positive inputs
(IN3–IN6) provide detector threshold voltages from
+0.5V to +3.05V in 10mV increments, or +1.0V to +5.5V
in 20mV increments.
The host controller communicates with the MAX6872/
MAX6873s’ internal 4kb user EEPROM, configuration
EEPROM, configuration registers, and fault registers
through an SMBus/I
2
C-compatible serial interface (see
Figure 1).
Programmable output options include active-high,
active-low, open-drain, weak pullup, push-pull, and
charge pump. Select the charge-pump output feature
to drive n-channel FETs for power-supply sequencing
(see the Applications Information section). The outputs
swing between 0 and (V
ABP
+ 5V) when configured for
charge-pump operation.
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
10 ______________________________________________________________________________________
COMPARATORS
REGISTER BANK
CONTROLLER
EEPROM
(USER AND
CONFIG)
OUTPUT
STAGES
LOGIC NETWORK
FOR PO_
WATCHDOG
TIMERS
GPI_
GPI_, MR,
MARGIN
PO_
IN_
SDA,
SCL
ANALOG
BLOCK
DIGITAL
BLOCK
SERIAL
INTERFACE
Figure 1. Top-Level Block Diagram
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
______________________________________________________________________________________ 11
MAX6872
MAX6873
1.25V
V
REF
IN2 DETECTOR
IN_ DETECTOR
IN1
IN2
IN3
IN4
IN5
(N.C.)
IN6
(N.C.)
IN3 DETECTOR
IN4 DETECTOR
IN5 DETECTOR
IN6 DETECTOR
PROGRAMMABLE
ARRAY
TIMING BLOCK 2
TIMING BLOCK 3
TIMING BLOCK 4
TIMING BLOCK 5
TIMING BLOCK 6
TIMING BLOCK 7
TIMING BLOCK 8
PO2 OUTPUT
PO3 OUTPUT
PO4 OUTPUT
PO5 OUTPUT
PO6 OUTPUT
PO7 OUTPUT
PO8 OUTPUT
TIMING BLOCK 1
V
ABP
+ 5V
CHARGE PUMP*
MUX
GPI1
GPI2
GPI3
GPI4
MARGIN
MR
IN3–IN6
(IN3–IN4)
PO_
OUTPUT
*PO1–PO4 ONLY
(PO1, PO2)
ABP
MUX
P1**
10k
PO1
PO2
PO3
PO4
PO5
PO6
(N.C.)
PO7
(N.C.)
PO8
(N.C.)
OPEN-
DRAIN
** PO5–PO8 ONLY
(PO3, PO4, PO5)
MAIN
OSCILLATOR
SERIAL
INTERFACE
SDA
SCL
A0
A1
EEPROM
CHARGE PUMP
CONFIG
REGISTERS
CONFIG
EEPROM
USER
EEPROM
1
µ
F
ABP
DBP
1
µ
F
2.55V
LDO
5.4V
LDO
(VIRTUAL
DIODES)
GND
( ) ARE FOR MAX6873 ONLY.
Functional Diagram
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
12 ______________________________________________________________________________________
Program each output to assert on any voltage-detector
input, general-purpose logic input, watchdog timer,
manual reset, or other output stages. Programmable
timing-delay blocks configure each output to wait
between 25µs and 1600ms before deasserting. A fault
register logs the conditions that caused each output to
assert (undervoltage, overvoltage, manual reset, etc.).
The MAX6872/MAX6873 feature two watchdog timers,
adding flexibility. Program each watchdog timer to assert
one or more programmable outputs. Program each
watchdog timer to clear on a combination of one GPI_
input and one programmable output, one of the GPI_
inputs only, or one of the programmable outputs only.
The initial and normal watchdog timeout periods are
independently programmable from 6.25ms to 102.4s.
A virtual diode-ORing scheme selects the input that pow-
ers the MAX6872/MAX6873. The MAX6872/MAX6873
derive power from IN1 if V
IN1
> +6.5V or from the highest
voltage on IN3–IN6 if V
IN1
< +2.7V. The power source
cannot be determined if +4V < V
IN1
< +6.5V and one
of V
IN3
through V
IN6
> +2.7V. The programmable out-
puts maintain the correct programmed logic state for
V
ABP
> V
UVLO
. One of IN3 through IN6 must be
greater than +2.7V or IN1 must be greater than +4V for
device operation.
Powering the MAX6872/MAX6873
The MAX6872/MAX6873 derive power from the positive
voltage-detector inputs: IN1 or IN3–IN6. A virtual diode-
ORing scheme selects the positive input that supplies
power to the device (see the Functional Diagram). IN1
must be at least +4V or one of IN3–IN6 (MAX6872)/
IN3–IN4 (MAX6873) must be at least +2.7V to ensure
device operation. An internal LDO regulates IN1 down
to +5.4V.
The highest input voltage on IN3–IN6 (MAX6872)/
IN3–IN4 (MAX6873) supplies power to the device, unless
V
IN1
+6.5V, in which case IN1 supplies power to the
device. For +4V < V
IN1
< +6.5V and one of V
IN3
through
V
IN6
> +2.7V, the input power source cannot be deter-
mined due to the dropout voltage of the LDO. Internal
hysteresis ensures that the supply input that initially pow-
ered the device continues to power the device when
multiple input voltages are within 50mV of each other.
ABP powers the analog circuitry; bypass ABP to GND
with a 1µF ceramic capacitor installed as close to the
device as possible. The internal supply voltage, mea-
sured at ABP, equals the maximum of IN3–IN6
(MAX6872)/IN3–IN4 (MAX6873) if V
IN1
= 0, or equals
+5.4V when V
IN1
> +6.5V. Do not use ABP to provide
power to external circuitry.
The MAX6872/MAX6873 also generate a digital supply
voltage (DBP) for the internal logic circuitry and the
EEPROM; bypass DBP to GND with a 1µF ceramic
capacitor installed as close to the device as possible.
The nominal DBP output voltage is +2.55V. Do not use
DBP to provide power to external circuitry.
Inputs
The MAX6872/MAX6873 contain multiple logic and volt-
age-detector inputs. Each voltage-detector input is
simultaneously monitored for primary and secondary
thresholds. The primary threshold must be an under-
voltage threshold. The secondary threshold may be an
undervoltage or overvoltage threshold. Table 1 summa-
rizes these various inputs.
Set the primary and secondary threshold voltages for
each voltage-detector input with registers 00h–0Bh.
Each primary threshold voltage must be an undervolt-
age threshold. Configure each secondary threshold
voltage as an undervoltage or overvoltage threshold
(see register 0Ch). Set the threshold range for each
voltage detector with register 0Dh.
High-Voltage Input (IN1)
IN1 offers threshold voltages of +2.5V to +13.2V in
50mV increments, or +1.25V to +7.625V in 25mV incre-
ments. Use the following equations to set the threshold
voltages for IN1:
where V
TH
is the desired threshold voltage and x is the
decimal code for the desired threshold (Table 2). For
the +2.5V to +13.2V range, x must equal 214 or less,
otherwise the threshold exceeds the maximum operat-
ing voltage of IN1.
Bipolar-Voltage Input (IN2)
IN2 offers negative thresholds from -2.5V to -15.25V in
50mV increments, or from -1.25V to -7.625V in 25mV
increments. Alternatively, IN2 offers positive thresholds
from +2.5V to +15.25V in 50mV increments, or +1.25V
to +7.625V in 25mV increments. Use the following
equations to set the threshold voltages for IN2:
x
VV
V
for V to V range
TH
=
()
−−
.
.
. .
25
005
2 5 15 25
x
VV
V
for V to V range
TH
=++
.
.
. .
125
0 025
1 25 7 625
x
VV
V
for V to V range
TH
=++
.
.
. .
25
005
2 5 13 2

MAX6872ETJ+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits EEPROM-Prog Hex Power-Sup Sequence
Lifecycle:
New from this manufacturer.
Delivery:
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