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MAX6872ETJ+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
22 ______________________________________________________________________________________
Table 12. PO4 (MAX6872)/PO2 (MAX6873) Output Dependency (Product 1)
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT OUTPUT ASSERTION CONDITIONS
[0] 1 = PO4/PO2 assertion depends on IN1 primary undervoltage threshold (Table 2).
[1] 1 = PO4/PO2 assertion depends on IN2 primary undervoltage threshold (Table 3).
[2] 1 = PO4/PO2 assertion depends on IN3 primary undervoltage threshold (Table 4).
[3] 1 = PO4/PO2 assertion depends on IN4 primary undervoltage threshold (Table 4).
[4]
1 = P O4 ( M AX 6872 onl y) asser ti on d ep end s on IN 5 p r i m ar y und er vol tag e thr eshol d ( Tab l e 4) .
M ust b e set to 0 for the M AX 6873.
[5]
1 = P O4 ( M AX 6872 onl y) asser ti on d ep end s on IN 6 p r i m ar y und er vol tag e thr eshol d ( Tab l e 4) .
M ust b e set to 0 for the M AX 6873.
[6] 1 = PO4/PO2 assertion depends on watchdog 1 (Tables 25 and 26).
1Dh 801Dh
[7] 1 = PO4/PO2 assertion depends on watchdog 2 (Tables 25 and 26).
[0] 1 = P O4/P O2 asser ti on d ep end s on IN 1 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 2) .
[1] 1 = P O4/P O2 asser ti on d ep end s on IN 2 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 3) .
[2] 1 = P O4/P O2 asser ti on d ep end s on IN 3 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[3] 1 = P O4/P O2 asser ti on d ep end s on IN 4 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[4]
1 = PO4 (MAX6872 only) assertion depends on IN5 secondary undervoltage/overvoltage
threshold (Table 4). Must be set to 0 for the MAX6873.
[5]
1 = PO4 (MAX6872 only) assertion depends on IN6 secondary undervoltage/overvoltage
threshold (Table 4). Must be set to 0 for the MAX6873.
[6] 1 = PO4/PO2 assertion depends on GPI1 (Table 5).
1Eh 801Eh
[7] 1 = PO4/PO2 assertion depends on GPI2 (Table 5).
[0] 1 = PO4/PO2 assertion depends on GPI3 (Table 5).
[1] 1 = PO4/PO2 assertion depends on GPI4 (Table 5).
[2] 1 = P O4 ( M AX 6872 onl y) asser ti on d ep end s on P O1 ( Tab l e 8) . M ust b e set to 0 for the M AX 6873.
[3] 1 = P O4 ( M AX 6872 onl y) asser ti on d ep end s on P O2 ( Tab l e 9) . M ust b e set to 0 for the M AX 6873.
[4] 1 = P O4/P O 2 asser ti on d ep end s on P O3 ( M AX 6872) /P O 1 ( M AX 6873) ( Tab l es 10 and 11) .
[5] 1 = P O4/P O 2 asser ti on d ep end s on P O5 ( M AX 6872) /P O 3 ( M AX 6873) ( Tab l es 14 and 15) .
[6] 1 = P O4/P O 2 asser ti on d ep end s on P O6 ( M AX 6872) /P O 4 ( M AX 6873) ( Tab l es 16 and 17) .
1Fh 801Fh
[7] 1 = PO4/PO2 assertion depends on PO7 (MAX6872)/PO5 (MAX6873) (Table 18).
23h 8023h [0] 1 = P O4 ( M AX 6872 onl y) asser ti on d ep end s on P O8 ( Tab l e 19) . M ust b e set to 0 for the M AX 6873.
40h 8040h [3] 1 = PO4/PO2 asserts when MR = low (Table 6).
Table 12 only applies to PO4 of the MAX6872 and PO2
of the MAX6873. Write a 0 to a bit to make the PO4/PO2
output independent of the respective signal (IN_ primary
or secondary thresholds, WD1 or WD2, GPI1–GPI4, MR,
or other programmable outputs). See Table 13 for
Product 2. PO4 (MAX6872)/PO2 (MAX6873) deasserts
when Product 1 or Product 2 = 1.
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
______________________________________________________________________________________ 23
Table 13 only applies to PO4 of the MAX6872 and PO2
of the MAX6873. Write a 0 to a bit to make the PO4/PO2
output independent of the respective signal (IN_ primary
or secondary thresholds, WD1 or WD2, GPI1 to GPI4,
MR, or other programmable outputs). See Table 12 for
Product 1. PO4 (MAX6872)/PO2 (MAX6873) deasserts
when Product 1 or Product 2 = 1.
Table 13. PO4 (MAX6872)/PO2 (MAX6873) Output Dependency (Product 2)
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT OUTPUT ASSERTION CONDITIONS
[0] 1 = PO4/PO2 assertion depends on IN1 primary undervoltage threshold (Table 2).
[1] 1 = PO4/PO2 assertion depends on IN2 primary undervoltage threshold (Table 3).
[2] 1 = PO4/PO2 assertion depends on IN3 primary undervoltage threshold (Table 4).
[3] 1 = PO4/PO2 assertion depends on IN4 primary undervoltage threshold (Table 4).
[4]
1 = PO4 (MAX6872 only) assertion depends on IN5 primary undervoltage threshold (Table 4).
Must be set to 0 for the MAX6873.
[5]
1 = PO4 (MAX6872 only) assertion depends on IN6 primary undervoltage threshold (Table 4).
Must be set to 0 for the MAX6873.
[6] 1 = PO4/PO2 assertion depends on watchdog 1 (Tables 25 and 26).
20h 8020h
[7] 1 = PO4/PO2 assertion depends on watchdog 2 (Tables 25 and 26).
[0] 1 = P O4/P O2 asser ti on d ep end s on IN 1 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 2) .
[1] 1 = P O4/P O2 asser ti on d ep end s on IN 2 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 3) .
[2] 1 = P O4/P O2 asser ti on d ep end s on IN 3 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[3] 1 = P O4/P O2 asser ti on d ep end s on IN 4 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[4]
1 = PO4 (MAX6872 only) assertion depends on IN5 secondary undervoltage/overvoltage
threshold (Table 4). Must be set to 0 for the MAX6873.
[5]
1 = PO4 (MAX6872 only) assertion depends on IN6 secondary undervoltage/overvoltage
threshold (Table 4). Must be set to 0 for the MAX6873.
[6] 1 = PO4/PO2 assertion depends on GPI1 (Table 5).
21h 8021h
[7] 1 = PO4/PO2 assertion depends on GPI2 (Table 5).
[0] 1 = PO4/PO2 assertion depends on GPI3 (Table 5).
[1] 1 = PO4/PO2 assertion depends on GPI4 (Table 5).
[2] 1 = P O4 ( M AX 6872 onl y) asser ti on d ep end s on P O1 ( Tab l e 8) . M ust b e set to 0 for the M AX 6873.
[3] 1 = P O4 ( M AX 6872 onl y) asser ti on d ep end s on P O2 ( Tab l e 9) . M ust b e set to 0 for the M AX 6873.
[4] 1 = PO4/PO2 assertion depends on PO3 (MAX6872)/PO1 (MAX6873) (Tables 10 and 11).
[5] 1 = PO4/PO2 assertion depends on PO5 (MAX6872)/PO3 (MAX6873) (Tables 14 and 15).
[6] 1 = PO4/PO2 assertion depends on PO6 (MAX6872)/PO4 (MAX6873) (Tables 16 and 17).
22h 8022h
[7] 1 = PO4/PO2 assertion depends on PO7 (MAX6872)/PO5 (MAX6873) (Table 18).
23h 8023h [1] 1 = P O4 ( M AX 6872 onl y) asser ti on d ep end s on P O8 ( Tab l e 19) . M ust b e set to 0 for the M AX 6873.
40h 8040h [3] 1 = PO4/PO2 asserts when MR = low (Table 6).
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
24 ______________________________________________________________________________________
Table 14. PO5 (MAX6872)/PO3 (MAX6873) Output Dependency (Product 1)
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT OUTPUT ASSERTION CONDITIONS
[0] 1 = PO5/PO3 assertion depends on IN1 primary undervoltage threshold (Table 2).
[1] 1 = PO5/PO3 assertion depends on IN2 primary undervoltage threshold (Table 3).
[2] 1 = PO5/PO3 assertion depends on IN3 primary undervoltage threshold (Table 4).
[3] 1 = PO5/PO3 assertion depends on IN4 primary undervoltage threshold (Table 4).
[4]
1 = PO5 (MAX6872 only) assertion depends on IN5 primary undervoltage threshold (Table 4).
Must be set to 0 for the MAX6873.
[5]
1 = PO5 (MAX6872 only) assertion depends on IN6 primary undervoltage threshold (Table 4).
Must be set to 0 for the MAX6873.
[6] 1 = PO5/PO3 assertion depends on watchdog 1 (Tables 25 and 26).
24h 8024h
[7] 1 = PO5/PO3 assertion depends on watchdog 2 (Tables 25 and 26).
[0] 1 = P O5/P O3 asser ti on d ep end s on IN 1 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 2) .
[1] 1 = P O5/P O3 asser ti on d ep end s on IN 2 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 3) .
[2] 1 = P O5/P O3 asser ti on d ep end s on IN 3 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[3] 1 = P O5/P O3 asser ti on d ep end s on IN 4 second ar y und er vol tag e/over vol tag e thr eshol d ( Tab l e 4) .
[4]
1 = PO5 (MAX6872 only) assertion depends on IN5 secondary undervoltage/overvoltage
threshold (Table 4). Must be set to 0 for the MAX6873.
[5]
1 = PO5 (MAX6872 only) assertion depends on IN6 secondary undervoltage/overvoltage
threshold (Table 4). Must be set to 0 for the MAX6873.
[6] 1 = PO5/PO3 assertion depends on GPI1 (Table 5).
25h 8025h
[7] 1 = PO5/PO3 assertion depends on GPI2 (Table 5).
[0] 1 = PO5/PO3 assertion depends on GPI3 (Table 5).
[1] 1 = PO5/PO3 assertion depends on GPI4 (Table 5).
[2] 1 = P O5 ( M AX 6872 onl y) asser ti on d ep end s on P O1 ( Tab l e 8) . M ust b e set to 0 for the M AX 6873.
[3] 1 = P O5 ( M AX 6872 onl y) asser ti on d ep end s on P O2 ( Tab l e 9) . M ust b e set to 0 for the M AX 6873.
[4] 1 = PO5/PO3 assertion depends on PO3 (MAX6872)/PO1 (MAX6873) (Tables 10 and 11).
[5] 1 = PO5/PO3 assertion depends on PO4 (MAX6872)/PO2 (MAX6873) (Tables 12 and 13).
[6] 1 = PO5/PO3 assertion depends on PO6 (MAX6872)/PO4 (MAX6873) (Tables 16 and 17).
26h 8026h
[7] 1 = PO5/PO3 assertion depends on PO7 (MAX6872)/PO5 (MAX6873) (Table 18).
2Ah 802Ah [0] 1 = P O5 ( M AX 6872 onl y) asser ti on d ep end s on P O8 ( Tab l e 19) . M ust b e set to 0 for the M AX 6873.
40h 8040h [4] 1 = PO5/PO3 asserts when MR = low (Table 6).
Table 14 only applies to PO5 of the MAX6872 and PO3
of the MAX6873. Write a 0 to a bit to make the PO5/PO3
output independent of the respective signal (IN_ primary
or secondary thresholds, WD1 or WD2, GPI1–GPI4, MR,
or other programmable outputs). See Table 15 for
Product 2. PO5 (MAX6872)/PO3 (MAX6873) deasserts
when Product 1 or Product 2 = 1.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

MAX6872ETJ+T

Mfr. #:
Buy MAX6872ETJ+T
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits EEPROM-Prog Hex Power-Sup Sequence
Lifecycle:
New from this manufacturer.
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