MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
______________________________________________________________________________________ 43
Forcing Programmable
Outputs High During Power-Up
A weak 10µA pulldown holds all programmable outputs
low during power-up until ABP exceeds the undervolt-
age lockout (UVLO) threshold. Applications requiring a
guaranteed high programmable output for ABP down to
GND require external pullup resistors to maintain the
logic state until ABP exceeds UVLO. Use 20k resis-
tors for most applications.
Driving High-Side MOSFET
Switches with the MAX6872/MAX6873
High-side MOSFET switches are commonly used in
power-supply sequencing applications. First, configure
the programmable output of the MAX6872/MAX6873 as
an active-low charge-pump output and set the condi-
tions to assert this output. Connect the programmable
output to the gate of an n-channel MOSFET. As the
conditions to deassert this output are met, the output
deasserts high (V
ABP
+5V), turning on the FET, thus
allowing the voltage on the drain to pass through to the
downstream device (see Figure 9).
Table 27. Fault Registers (60h–62h)
REGISTER
ADDRESS
BIT
RANGE
DESCRIPTION
[0] 1 = IN1 falls below primary undervoltage threshold.
[1] 1 = IN2 falls below primary undervoltage threshold.
[2] 1 = IN3 falls below primary undervoltage threshold.
[3] 1 = IN4 falls below primary undervoltage threshold.
[4] 1 = IN5 (MAX6872 only) falls below primary undervoltage threshold.
[5] 1 = IN6 (MAX6872 only) falls below primary undervoltage threshold.
60h
[7:6] Not used.
[0]
1 = IN1 falls below secondary undervoltage threshold or rises above secondary overvoltage threshold,
depending on the settings in register 0Ch (see Tables 2, 3, and 4).
[1]
1 = IN2 falls below secondary undervoltage threshold or rises above secondary overvoltage threshold,
depending on the settings in register 0Ch (see Tables 2, 3, and 4).
[2]
1 = IN3 falls below secondary undervoltage threshold or rises above secondary overvoltage threshold,
depending on the settings in register 0Ch (see Tables 2, 3, and 4).
[3]
1 = IN4 falls below secondary undervoltage threshold or rises above secondary overvoltage threshold,
depending on the settings in register 0Ch (see Tables 2, 3, and 4).
[4]
1 = IN5 (MAX6872 only) falls below secondary undervoltage threshold or rises above secondary
overvoltage threshold, depending on the settings in register 0Ch (see Tables 2, 3, and 4).
[5]
1 = IN6 (MAX6872 only) falls below secondary undervoltage threshold or rises above secondary
overvoltage threshold, depending on the settings in register 0Ch (see Tables 2, 3, and 4).
61h
[7:6] Not used.
[0] 1 = WD1 asserted.
[1] 1 = WD2 asserted.
[2] 1 = GPI1 asserted.
[3] 1 = GPI2 asserted.
[4] 1 = GPI3 asserted.
[5] 1 = GPI4 asserted.
[6] 1 = MR asserted.
62h
[7] Not used.
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
44 ______________________________________________________________________________________
Uses for General-Purpose Inputs
(GPI1–GPI4)
Watchdog Timer
Program GPI_ as an input to one of the watchdog
timers in the MAX6872/MAX6873. The GPI_ input must
toggle within the watchdog timeout period, otherwise
any programmable output dependent on the watchdog
timer asserts.
Additional Manual Reset Functions
The PO7 (MAX6872)/PO5 (MAX6873) programmable
outputs allow a single set (product 1 only) of conditions
to assert the output. Program the set of conditions to
depend on one of the GPI_ inputs. Any output that
depends on GPI_ asserts when GPI_ is held in its
active state, effectively acting as a manual reset input.
IN3 PO1
TO
LOAD
+5V
GND
MAX6872
MAX6873
Figure 9. Driving High-Side n-Channel MOSFET Switches
Table 28. Configuration Lock Register
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT
RANGE
DESCRIPTION
[0]
0 = configuration unlocked.
1 = configuration locked.
45h 8045h
[7:1] Not used.
Table 29. Write Disable Register
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT
RANGE
DESCRIPTION
[0]
0 = write not disabled if PO1 asserts (MAX6872).
1 = write disabled if PO1 asserts (MAX6872). Set to 0 (MAX6873).
[1]
0 = write not disabled if PO2 asserts (MAX6872).
1 = write disabled if PO2 asserts (MAX6872). Set to 0 (MAX6873).
[2]
0 = write not disabled if PO3 (MAX6872)/PO1 (MAX6873) asserts.
1 = write disabled if PO3 (MAX6872)/PO1 (MAX6873) asserts.
[3]
0 = write not disabled if PO4 (MAX6872)/PO2 (MAX6873) asserts.
1 = write disabled if PO4 (MAX6872)/PO2 (MAX6873) asserts.
[4]
0 = write not disabled if PO5 (MAX6872)/PO3 (MAX6873) asserts.
1 = write disabled if PO5 (MAX6872)/PO3 (MAX6873) asserts.
[5]
0 = write not disabled if PO6 (MAX6872)/PO4 (MAX6873) asserts.
1 = write disabled if PO6 (MAX6872)/PO4 (MAX6873) asserts.
[6]
0 = write not disabled if PO7 (MAX6872)/PO5 (MAX6873) asserts.
1 = write disabled if PO7 (MAX6872)/PO5 (MAX6873) asserts.
43h 8043h
[7]
0 = write not disabled if PO8 asserts (MAX6872).
1 = write disabled if PO8 asserts (MAX6872). Set to 0 (MAX6873).
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
______________________________________________________________________________________ 45
32
31
30
29
28
27
26
PO1
I.C.
IN1
IN2
IN3
IN4
IN5
25 IN6
9
10
11
12
13
14
15
N.C.
N.C.
MARGIN
MR
SDA
SCL
A0
16A1
17
18
19
20
21
22
23
GPI4
*EXPOSED PADDLE INTERNALLY CONNECTED TO GND.
*EXPOSED PADDLE
GPI3
GPI2
GPI1
ABP
DBP
N.C.
8
7
6
5
4
3
2
PO8
PO7
PO6
PO5
GND
PO4
PO3
MAX6872
(7mm x 7mm Thin QFN)
1PO2
24 N.C.
TOP VIEW
32
31
30
29
28
27
26
N.C.
I.C.
IN1
IN2
IN3
IN4
N.C.
25 N.C.
9
10
11
12
13
14
15
N.C.
N.C.
MARGIN
MR
SDA
SCL
A0
16A1
17
18
19
20
21
22
23
GPI4
*EXPOSED PADDLE
GPI3
GPI2
GPI1
ABP
DBP
N.C.
8
7
6
5
4
3
2
N.C.
PO5
PO4
PO3
GND
PO2
PO1
MAX6873
(7mm x 7mm Thin QFN)
1N.C.
24 N.C.
Pin Configurations
Selector Guide
PART
VOLTAGE-DETECTOR
INPUTS
GENERAL-PURPOSE INPUTS
PROGRAMMABLE
OUTPUTS
MAX6872ETJ 6 4 8
MAX6873ETJ 4 4 5
Other Fault Signals from µC
Connect a general-purpose output from a µC to one of
the GPI_ inputs to allow interrupts to assert any output
of the MAX6872/MAX6873. Configure one of the pro-
grammable outputs to assert on whichever GPI_ input
connects to the general-purpose output of the µC.
Layout and Bypassing
For better noise immunity, bypass each of the voltage
detector inputs to GND with 0.1µF capacitors installed
as close to the device as possible. Bypass ABP and
DBP to GND with 1µF capacitors installed as close to
the device as possible. ABP and DBP are internally
generated voltages and should not be used to supply
power to external circuitry.
Configuration Latency Period
A delay of less than 5µs occurs between writing to the
configuration registers and the time when these
changes actually take place, except when changing
one of the voltage-detector thresholds. Changing a volt-
age-detector threshold typically takes 150µs. When
changing EEPROM contents, a software reboot or
cycling of power is required for these changes to trans-
fer to volatile memory.

MAX6872ETJ+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits EEPROM-Prog Hex Power-Sup Sequence
Lifecycle:
New from this manufacturer.
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