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MAX6872ETJ+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
34 ______________________________________________________________________________________
SA7 through SA4 represent the standard interface
address (1010) for devices with EEPROM. SA3 and SA2
correspond to the A1 and A0 address inputs of the
MAX6872/MAX6873 (hard-wired as logic-low or logic-
high). SA0 is a read/write flag bit (0 = write, 1 = read).
The A0 and A1 address inputs allow up to four
MAX6872/MAX6873 devices to connect to one bus.
Connect A0 and A1 to GND or to the serial interface
power supply (see Figure 6).
Send Byte
The send byte protocol allows the master device to send
one byte of data to the slave device (see Figure 7). The
send byte presets a register pointer address for a sub-
sequent read or write. The slave sends a NACK instead
of an ACK if the master tries to send an address that is
not allowed. If the master sends 80h, 81h, or 82h, the
data is ACK. This could be start of the write byte/word
protocol, and the slave expects at least one further
data byte. If the master sends a stop condition, the
internal address pointer does not change. If the master
sends 84h, this signifies that the block read protocol is
expected, and a repeated start condition should follow.
The device reboots if the master sends 88h. The send
byte procedure follows:
1) The master sends a start condition.
2) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit data byte.
5) The addressed slave asserts an ACK on SDA.
6) The master sends a stop condition.
Write Byte/Word
The write byte/word protocol allows the master device
to write a single byte in the register bank, preset an
EEPROM (configuration or user) address for a subse-
quent read, or to write a single byte to the configuration
or user EEPROM (see Figure 7). The write byte/word
procedure follows:
1) The master sends a start condition.
2) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit command code.
5) The addressed slave asserts an ACK on SDA.
6) The master sends an 8-bit data byte.
7) The addressed slave asserts an ACK on SDA.
8) The master sends a stop condition or sends another
8-bit data byte.
9) The addressed slave asserts an ACK on SDA.
10)The master sends a stop condition.
To write a single byte to the register bank, only the 8-bit
command code and a single 8-bit data byte are sent.
The command code must be in the range of 00h to 45h.
The data byte is written to the register bank if the com-
mand code is valid. The slave generates a NACK at
step 5 if the command code is invalid.
To preset an EEPROM (configuration or user) address
for a subsequent read, the 8-bit command code and a
single 8-bit data byte are sent. The command code
must be 80h if the write is to be directed into the config-
uration EEPROM, or 81h or 82h, if the write is to be
SDA
SCL
1
MSB LSBSTART
01
0
A1
A0
X R/W
ACK
Figure 6. Slave Address
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
______________________________________________________________________________________ 35
WRITE BYTE FORMAT
S
S
ADDRESS
ADDRESS
7 bits
7 bits
SEND BYTE FORMAT
RECEIVE BYTE FORMAT
WR
WR
ACK
ACK
DATA
DATA
8 bits
8 bits
ACK P
ACK P
Data Byte–presets the
internal address pointer.
Data Byte–reads data from
the register commanded by
the last read byte or write
byte transmission. Also
dependent on a send byte.
WRITE WORD FORMAT
S ADDRESS WR
ACK ACK ACK ACKCOMMAND DATA DATA P
7 bits 8 bits 8 bits 8 bits
Slave Address–
equivalent to chip-
select line of a 3-
wire interface.
Command Byte–
MSB of the
EEPROM
register being
written.
Data Byte–first byte is the LSB of
the EEPROM address. Second
byte is the actual data.
BLOCK WRITE FORMAT
S ADDRESS WR
ACK COMMAND ACK
BYTE
COUNT= N
ACK
DATA BYTE
1
ACK
DATA BYTE
...
ACK
DATA BYTE
N
ACK P
7 bits 83h 8 bits 8 bits 8 bits
Slave Address–
equivalent to chip-
select line of a 3-
wire interface.
Command Byte–
prepares device
for block
operation.
Data Byte–data goes into the register set by the
command byte.
BLOCK READ FORMAT
S ADDRESS WR ACK COMMAND ACK SR ADDRESS WR ACK
8 bits
BYTE
COUNT= 16
ACK
DATA BYTE
1
ACK
DATA BYTE
...
ACK
DATA BYTE
N
ACK P
7 bits 84h 7 bits 10h 8 bits8 bits 8 bits
Slave Address–
equivalent to chip-
select line of a 3-
wire interface.
Command Byte–
prepares device
for block
operation.
Slave Address–
equivalent to chip-
select line of a 3-
wire interface.
Data Byte–data goes into the register set by the
command byte.
S = Start condition.
P = Stop condition.
Shaded = Slave transmission.
SR = Repeated start condition.
Slave Address–
equivalent to chip-
select line of a 3-
wire interface.
Slave Address–
equivalent to chip-
select line of a 3-
wire interface.
S ADDRESS WR ACK COMMAND ACK DATA ACK P
7 bits 8 bits 8 bits
Slave Address–
equivalent to chip-
select line of a 3-
wire interface.
Command Byte–
selects register
being written.
Data Byte–data goes into the
register set by the command
byte if the command is below
50h. If the command is 80h,
81h, or 82h, the data byte
presets the LSB of an EEPROM
address.
10
0
00
10
Figure 7. SMBus/I
2
C Protocols
MAX6872/MAX6873
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
36 ______________________________________________________________________________________
directed into the user EEPROM. If the command code is
80h, the data byte must be in the range of 00h to 45h. If
the command code is 81h or 82h, the data byte can be
00h to FFh. A NACK is generated in step 7 if none of the
above conditions are true.
To write a single byte of data to the user or configuration
EEPROM, the 8-bit command code and a single 8-bit
data byte are sent. The following 8-bit data byte is writ-
ten to the addressed EEPROM location.
Block Write
The block write protocol allows the master device to
write a block of data (1 to 16 bytes) to the EEPROM or
to the register bank (see Figure 7). The destination
address must already be set by the send byte or write
byte protocol and the command code must be 83h. If
the number of bytes to be written causes the address
pointer to exceed 45h for the configuration register or
configuration EEPROM, the address pointer stays at
45h, overwriting this memory address with the remain-
ing bytes of data. The last data byte sent is stored at
register address 45h. If the number of bytes to be writ-
ten exceeds the address pointer FFh for the user EEP-
ROM, the address pointer loops back to 00h, and
continues writing bytes until all data is written. The
block write procedure follows:
1) The master sends a start condition.
2) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends the 8-bit command code for
block write (83h).
5) The addressed slave asserts an ACK on SDA.
6) The master sends the 8-bit byte count (1 to 16 bytes) N.
7) The addressed slave asserts an ACK on SDA.
8) The master sends 8 bits of data.
9) The addressed slave asserts an ACK on SDA.
10) Repeat steps 8 and 9 one time.
11) The master generates a stop condition.
Receive Byte
The receive byte protocol allows the master device to
read the register content of the MAX6872/MAX6873
(see Figure 7). The EEPROM or register address must
be preset with a send byte or write word protocol first.
Once the read is complete, the internal pointer increas-
es by one. Repeating the receive byte protocol reads
the contents of the next address. The receive byte pro-
cedure follows:
1) The master sends a start condition.
2) The master sends the 7-bit slave address and a
read bit (high).
3) The addressed slave asserts an ACK on SDA.
4) The slave sends 8 data bits.
5) The master asserts a NACK on SDA.
6) The master generates a stop condition.
Block Read
The block read protocol allows the master device to
read a block of 16 bytes from the EEPROM or register
bank (see Figure 7). Read fewer than 16 bytes of data
by issuing an early STOP condition from the master, or
by generating a NACK with the master. The send byte
or write byte protocol predetermines the destination
address with a command code of 84h. The block read
procedure follows:
1) The master sends a start condition.
2) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends 8 bits of the block read command
(84h).
5) The slave asserts an ACK on SDA, unless busy.
6) The master generates a repeated start condition.
7) The master sends the 7-bit slave address and a
read bit (high).
8) The slave asserts an ACK on SDA.
9) The slave sends the 8-bit byte count (16).
10)The master asserts an ACK on SDA.
11)The slave sends 8 bits of data.
12)The master asserts an ACK on SDA.
13)Repeat steps 8 and 9 fifteen times.
14)The master generates a stop condition.
Address Pointers
Use the send byte protocol to set the register address
pointers before read and write operations. For the con-
figuration registers, valid address pointers range from
00h to 45h. Register addresses outside of this range
result in a NACK being issued from the MAX6872/
MAX6873. When using the block write protocol, the
address pointer automatically increments after each
data byte, except when the address pointer is already
at 45h. If the address pointer is already 45h, and more
data bytes are being sent, these subsequent bytes
overwrite address 45h repeatedly, leaving only the last
data byte sent stored at this register address.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

MAX6872ETJ+T

Mfr. #:
Buy MAX6872ETJ+T
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits EEPROM-Prog Hex Power-Sup Sequence
Lifecycle:
New from this manufacturer.
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