SPC563M64L5COBR Datasheet SPC563M64L7COAY, SPC563M64L5COAY, SPC563M64L7COAR | P22-P24

Device overview SPC563Mxx

22/48 Doc ID 13850 Rev 6

For high priority interrupt requests, the time from the assertion of the interrupt request from

the peripheral to when the processor is executing the interrupt service routine (ISR) has

been minimized. The INTC provides a unique vector for each interrupt request source for

quick determination of which ISR needs to be executed. It also provides an ample number of

priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To

allow the appropriate priorities for each source of interrupt request, the priority of each

interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be

supported. The INTC supports the priority ceiling protocol for coherent accesses. By

providing a modifiable priority mask, the priority can be raised temporarily so that all tasks

which share the resource can not preempt each other.

Multiple processors can assert interrupt requests to each other through software setable

interrupt requests. These same software setable interrupt requests also can be used to

break the work involved in servicing an interrupt request into a high priority portion and a low

priority portion. The high priority portion is initiated by a peripheral interrupt request, but

then the ISR asserts a software setable interrupt request to finish the servicing in a lower

priority ISR. Therefore these software setable interrupt requests can be used instead of the

peripheral ISR scheduling a task through the RTOS.

The INTC provides the following features:

● 356 peripheral interrupt request sources

● 8 software setable interrupt request sources

● 9-bit vector addresses

● Unique vector for each interrupt request source

● Hardware connection to processor or read from register

● Each interrupt source can be programmed to one of 16 priorities

● Preemptive prioritized interrupt requests to processor

● ISR at a higher priority preempts executing ISRs or tasks at lower priorities

● Automatic pushing or popping of preempted priority to or from a LIFO

● Ability to modify the ISR or task priority to implement the priority ceiling protocol for

accessing shared resources

● Low latency—three clocks from receipt of interrupt request from peripheral to interrupt

request to processor

This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and

multiplexing logic.

3.3.5 FMPLL

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 20 MHz

crystal oscillator or external clock generator. Further, the FMPLL supports programmable

frequency modulation of the system clock. The PLL multiplication factor, output clock divider

ratio are all software configurable.

SPC563Mxx Device overview

Doc ID 13850 Rev 6 23/48

The PLL has the following major features:

● Input clock frequency from 4 MHz to 20 MHz

● Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz, resulting in

system clock frequencies from 16 MHz to 80 MHz with granularity of 4 MHz or better

● Reduced frequency divider (RFD) for reduced frequency operation without forcing the

PLL to relock

● 3 modes of operation

– Bypass mode with PLL off

– Bypass mode with PLL running (default mode out of reset)

– PLL normal mode

● Each of the three modes may be run with a crystal oscillator or an external clock

reference

● Programmable frequency modulation

– Modulation enabled/disabled through software

– Triangle wave modulation up to 100 kHz modulation frequency

– Programmable modulation depth (0% to 2% modulation depth)

– Programmable modulation frequency dependent on reference frequency

● Lock detect circuitry reports when the PLL has achieved frequency lock and

continuously monitors lock status to report loss of lock conditions

● Clock Quality Module

– detects the quality of the crystal clock and cause interrupt request or system reset

if error is detected

– detects the quality of the PLL output clock. If an error is detected, causes a system

reset or switches the system clock to the crystal clock and causes an interrupt

request

● Programmable interrupt request or system reset on loss of lock

3.3.6 Calibration EBI

The Calibration EBI controls data transfer across the crossbar switch to/from memories or

peripherals attached to the calibration tool connector in the calibration address space. The

Calibration EBI is only available in the calibration tool. The Calibration EBI includes a

memory controller that generates interface signals to support a variety of external

memories. The Calibration EBI memory controller supports legacy flash, SRAM, and

asynchronous memories. In addition, the calibration EBI supports up to three regions via

chip selects (two chip selects are multiplexed with two address bits), along with programmed

region-specific attributes. The calibration EBI supports the following features:

● 22-bit address bus (two most significant signals multiplexed with two chip selects)

● 16-bit data bus

● Multiplexed mode with addresses and data signals present on the data lines

Device overview SPC563Mxx

24/48 Doc ID 13850 Rev 6

Note: The calibration EBI must be configured in multiplexed mode when the extended Nexus trace

is used on the VertiCal Calibration Systemcalibration tool. This is because Nexus signals

and address lines of the calibration bus share the same balls in the calibration package.

● Memory controller with support for various memory types:

– Asynchronous/legacy flash and SRAM

● Bus monitor

– User selectable

– Programmable time-out period (with 8 external bus clock resolution)

● Configurable wait states (via chip selects)

● 3 chip-select (Cal_CS[0], Cal_CS[2:3]) signals (Multiplexed with 2 most significant

address signals)

● 2 write/byte enable (WE[0:1]/BE[0:1]) signals

● Configurable bus speed modes

– system frequency

– 1/2 of system frequency

– 1/4 of system frequency

● Optional automatic CLKOUT gating to save power and reduce EMI

● Selectable drive strengths; 10 pF, 20 pF, 30 pF, 50 pF

3.3.7 SIU

The SPC563Mxx SIU controls MCU reset configuration, pad configuration, external

interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset

operation. The reset configuration block contains the external pin boot configuration logic.

The pad configuration block controls the static electrical characteristics of I/O pins. The

GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.

The reset controller performs reset monitoring of internal and external reset sources, and

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SPC563M64L5COBR

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Manufacturer:

STMicroelectronics

Description:

32-bit Microcontrollers - MCU 32-bit Pwr Architect MCU Auto PwrTrainApp

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SPC563M64L5COBR

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