SPC563Mxx Device overview
Doc ID 13850 Rev 6 33/48
bound for the same ADC, the higher priority Queue is always served first
– Queue_0 can bypass all prioritization, buffering and abort current conversions to
start a Queue_0 conversion a deterministic time after the queue trigger
– Streaming mode operation of Queue_0 to execute some commands several times
– Supports software and hardware trigger modes to arm a particular Queue
– Generates interrupt when command coherency is not achieved
● External hardware triggers
– Supports rising edge, falling edge, high level and low level triggers
– Supports configurable digital filter
● Supports four external 8-to-1 muxes which can expand the input channels to 56
channels total
3.3.15 DSPI
The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface
for communication between the SPC563Mxx MCU and external devices. The DSPI supports
pin count reduction through serialization and deserialization of eTPU and eMIOS channels
and memory-mapped registers. The channels and register content are transmitted using a
SPI-like protocol. This SPI-like protocol is completely configurable for baud rate, polarity and
phase, frame length, chip select assertion, etc. Each bit in the frame may be configured to
serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI can be
configured to serialize data to an external device that supports the Microsecond Channel
protocol. There are two identical DSPI blocks on the SPC563Mxx MCU. The DSPI ouput
pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) according to the
Microsecond Channel specification.
The DSPIs have three configurations:
● Serial Peripheral Interface (SPI) configuration where the DSPI operates as an up to 16-
bit SPI with support for queues
● Enhanced Deserial Serial Interface (DSI) configuration where DSPI serializes up to 32
bits with three possible sources per bit
– eTPU, eMIOS, new virtual GPIO registers as possible bit source
– Programmable inter-frame gap in continuous mode
– Bit source selection allows microsecond channel downstream with command or
data frames up to 32 bits
– Microsecond channel dual receiver mode
● Combined Serial Interface (CSI) configuration where the DSPI operates in both SPI
and DSI configurations interleaving DSI frames with SPI frames, giving priority to SPI
frames
For queued operations, the SPI queues reside in system memory external to the DSPI. Data
transfers between the memory and the DSPI FIFOs are accomplished through the use of
the eDMA controller or through host software.
