OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

SPC563M64L5COBR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
Device overview SPC563Mxx
28/48 Doc ID 13850 Rev 6
The eMIOS provides the following features:
● 16 channels (24-bit timer resolution)
● For compatibility with other family members selected channels and timebases are
implemented:
– Channels 0 to 6, 8 to 15, and 23
– Timebases A, B and C
● Channels 1, 3, 5 and 6 support modes:
– General Purpose Input/Output (GPIO)
– Single Action Input Capture (SAIC)
– Single Action Output Compare (SAOC)
● Channels 2, 4, 11 and 13 support all the modes above plus:
– Output Pulse Width Modulation Buffered (OPWMB)
● Channels 0, 8, 9, 10, 12, 14, 15, 23 support all the modes above plus:
– Input Period Measurement (IPM)
– Input Pulse Width Measurement (IPWM)
– Double Action Output Compare (set flag on both matches) (DAOC)
– Modulus Counter Buffered (MCB)
– Output Pulse Width and Frequency Modulation Buffered (OPWFMB)
● Three 24-bit wide counter buses
– Counter bus A can be driven by channel 23 or by the eTPU2 and all channels can
use it as a reference
– Counter bus B is driven by channel 0 and channels 0 to 6 can use it as a reference
– Counter bus C is driven by channel 8 and channels 8 to 15 can use it as a
reference
● Shared time bases with the eTPU2 through the counter buses
● Synchronization among internal and external time bases
3.3.13 eTPU2
The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel
with the host CPU, eTPU2 processes instructions and real-time input events, performs
output waveform generation, and accesses shared data without host intervention.
Consequently, for each timer event, the host CPU setup and service times are minimized or
eliminated. A powerful timer subsystem is formed by combining the eTPU2 with its own
instruction and data RAM. High level assembler/compiler and documentation allows
customers to develop their own functions on the eTPU2.
SPC563Mxx Device overview
Doc ID 13850 Rev 6 29/48
The eTPU2 includes these distinctive features:
● The Timer Counter (TCR1), channel logic and digital filters (both channel and the
external timer clock input [TCRCLK]) now have an option to run at full system clock
speed or system clock / 2.
● Channels support unordered transitions: transition 2 can now be detected before
transition 1. Related to this enhancement, the transition detection latches (TDL1 and
TDL2) can now be independently negated by microcode.
● A new User Programmable Channel Mode has been added: the blocking, enabling,
service request and capture characteristics of this channel mode can be programmed
via microcode.
● Microinstructions now provide an option to issue Interrupt and Data Transfer requests
selected by channel. They can also be requested simultaneously at the same
instruction.
● Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the
entry point.
● Channel digital filters can be bypassed.
● The Timer Counter (TCR1), channel logic and digital filters (both channel and the
external timer clock input [TCRCLK]) now have an option to run at full system clock
speed or system clock / 2.
● Channels support unordered transitions: transition 2 can now be detected before
transition 1. Related to this enhancement, the transition detection latches (TDL1 and
TDL2) can now be independently negated by microcode.
● A new User Programmable Channel Mode has been added: the blocking, enabling,
service request and capture characteristics of this channel mode can be programmed
via microcode.
● Microinstructions now provide an option to issue Interrupt and Data Transfer requests
selected by channel. They can also be requested simultaneously at the same
instruction.
● Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the
entry point.
● Channel digital filters can be bypassed.
● 32 channels, each channel is associated with one input and one output signal
– Enhanced input digital filters on the input pins for improved noise immunity.
– Identical, orthogonal channels: each channel can perform any time function. Each
time function can be assigned to more than one channel at a given time, so each
signal can have any functionality.
– Each channel has an event mechanism which supports single and double action
functionality in various combinations. It includes two 24-bit capture registers, two
24-bit match registers, 24-bit greater-equal and equal-only comparators
– Input and output signal states visible from the host
● 2 independent 24-bit time bases for channel synchronization:
– First time base clocked by system clock with programmable prescale division from
2 to 512 (in steps of 2), or by output of second time base prescaler
– Second time base counter can work as a continuous angle counter, enabling
angle based applications to match angle instead of time
– Both time bases can be exported to the eMIOS timer module
– Both time bases visible from the host
Device overview SPC563Mxx
30/48 Doc ID 13850 Rev 6
● Event-triggered microengine:
– Fixed-length instruction execution in two-system-clock microcycle
– 14 KB of code memory (SCM)
– 3 KB of parameter (data) RAM (SPRAM)
– Parallel execution of data memory, ALU, channel control and flow control sub-
instructions in selected combinations
– 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and
subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte
operands, single-bit manipulation, shift operations, sign extension and conditional
execution
– Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned
Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit
works in parallel with the regular microcode commands
● Resource sharing features support channel use of common channel registers, memory
and microengine time:
– Hardware scheduler works as a “task management” unit, dispatching event
service routines by predefined, host-configured priority
– Automatic channel context switch when a “task switch” occurs, i.e., one function
thread ends and another begins to service a request from other channel: channel-
specific registers, flags and parameter base address are automatically loaded for
the next serviced channel
– SPRAM shared between host CPU and eTPU2, supporting communication either
between channels and host or inter-channel
– Dual-parameter coherency hardware support allows atomic access to two
parameters by host
● Test and development support features:
– Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction
execution, hardware breakpoints and watchpoints on several conditions
– Software breakpoints
– SCM continuous signature-check built-in self test (MISC — multiple input
signature calculator), runs concurrently with eTPU2 normal operation
● System enhancements
– Software watchdog with programmable timeout
– Real-time performance information
● Channel enhancements
– Channels 1 and 2 can optionally drive angle clock hardware
● Programming enhancements
– Engine relative addressing mode
3.3.14 eQADC
The enhanced queued analog to digital converter (eQADC) block provides accurate and fast
conversions for a wide range of applications. The eQADC provides a parallel interface to two
on-chip analog to digital converters (ADC), and a single master to single slave serial
interface to an off-chip external device. Both on-chip ADCs have access to all the analog
channels.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

SPC563M64L5COBR

Mfr. #:
Buy SPC563M64L5COBR
Manufacturer:
STMicroelectronics
Description:
32-bit Microcontrollers - MCU 32-bit Pwr Architect MCU Auto PwrTrainApp
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet