2000 Jul 31 12
NXP Semiconductors Product specification
Audio CODEC UDA1342TS
8.11 Sampling speed
The UDA1342TS operates with sample frequencies from
16 to 110 kHz. This range holds for the CODEC as a
whole. The DAC part can be configured in the L3-bus and
I
2
C-bus mode to accept 2 times and even 4 times the data
speed (e.g. f
s
is 96 or 192 kHz), but in these modes not all
of the features can be used.
Some examples of the input oversampling rate settings are
shown in Table 4.
Important: in the double speed mode an input signal of
0 dB is allowed, but in the quad speed mode the input
signal must be limited to −6 dB to prevent the system from
clipping.
Table 4 Examples of the input oversampling rate settings
SYSTEM CLOCK
SYSTEM
CLOCK
FREQUENCY
SETTING
SAMPLING
FREQUENCY
(kHz)
INPUT OVER-
SAMPLING
RATE
FEATURES SUPPORTED
12.288 MHz (256 × 48 kHz) 256f
s
48 single speed all
96 double speed only master volume and mute
192 quad speed no features
22.5792 MHz (512 × 44.1 kHz) 512f
s
44.1 single speed all
256f
s
88.2 single speed all
176.4 double speed only master volume and mute
33.8688 MHz (768 × 44.1 kHz) 768f
s
44.1 single speed all
384f
s
88.2 single speed all
176.4 double speed only master volume and mute
8.12 Power-on reset
The UDA1342TS has an internal Power-on reset circuit
(see Fig.7) which resets the test control block. All the
digital sound processing features and the system
controlling features are set to their default setting in the
L3-bus and I
2
C-bus mode.
The reset time (see Fig.8) is determined by an external
capacitor which is connected between pin V
ref
and ground.
The reset time should be at least 1 μs for V
ref
< 1.25 V.
When V
DDA(DAC)
is switched off, the device will be reset
again for V
ref
<0.75V.
During the reset time the system clock should be running.
handbook, halfpage
V
DDA(DAC)
V
ref
3.0 V
25
28
MGU001
UDA1342TS
C1 >
10 μF
RESET
CIRCUIT
8 kΩ
8 kΩ
Fig.7 Power-on reset circuit.
