2000 Jul 31 7
NXP Semiconductors Product specification
Audio CODEC UDA1342TS
7 PINNING
SYMBOL PIN TYPE DESCRIPTION
V
SSA(ADC)
1 analog ground pad ADC analog ground
VINL1 2 analog input pad ADC input left 1
V
DDA(ADC)
3 analog supply pad ADC analog supply voltage
VINR1 4 analog input pad ADC input right 1
V
ADCN
5 analog pad ADC reference voltage N
VINL2 6 analog input pad ADC input left 2
V
ADCP
7 analog pad ADC reference voltage P
VINR2 8 analog input pad ADC input right 2
IPSEL 9 5 V tolerant digital input pad channel select input: input left 1 and right 1 or
input left 2 and right 2
V
DDD
10 digital supply pad digital supply voltage
V
SSD
11 digital ground pad digital ground
SYSCLK 12 5 V tolerant digital input pad system clock input: 256f
s
,384f
s
,512f
s
or 768f
s
L3MODE 13 5 V tolerant digital input pad L3-bus mode input or mode selection input
L3CLOCK 14 5 V tolerant digital input pad L3-bus/I
2
C-bus clock input or clock selection
input
L3DATA 15 5 V tolerant open drain input/output L3-bus/I
2
C-bus data input/output or format
selection input
BCK 16 5 V tolerant digital input pad bit clock input
WS 17 5 V tolerant digital input pad word select input
DATAO 18 5 V tolerant 2 mA slew rate controlled digital
output
data output
DATAI 19 5 V tolerant digital input pad data input
TEST1 20 5 V tolerant digital input pad test control input; to be connected to ground
STATIC 21 5 V tolerant digital input pad mode selection input: static pin control or
L3-bus/I
2
C-bus control
STATUS 22 5 V tolerant 2 mA slew rate controlled digital
output
general purpose output
QMUTE 23 5 V tolerant digital input pad quick mute input
VOUTR 24 analog output pad DAC output right
V
DDA(DAC)
25 analog supply pad DAC analog supply voltage
VOUTL 26 analog output pad DAC output left
V
SSA(DAC)
27 analog ground pad DAC analog ground
V
ref
28 analog pad reference voltage for ADC and DAC
2000 Jul 31 8
NXP Semiconductors Product specification
Audio CODEC UDA1342TS
8 FUNCTIONAL DESCRIPTION
8.1 System clock
The UDA1342TS operates in slave mode only, this means
that in all applications the system must provide the system
clock. The system clock frequency is selectable and
depends on the mode of operation:
L3-bus/I
2
C-bus mode: 256f
s
, 384f
s
, 512f
s
or 768f
s
Static pin mode: 256f
s
or 384f
s
.
The system clock must be locked in frequency to the digital
interface signals.
Remarks:
The bit clock frequency f
BCK
can be up to 128f
s
, or in
other words the bit clock frequency is 128 times the
word select frequency f
WS
or less: f
BCK
128f
WS
The WS edge MUST fall on the negative edge of the
BCK signal at all times for proper operation of the digital
interface
The UDA1342TS operates with sample frequencies
from 16 to 110 kHz, however for a system clock of 768f
s
the sampling frequency must be limited to 55 kHz.
8.2 ADC analog front-end
The analog front-end of the UDA1342TS consists of two
stereo ADCs with a programmable gain stage (gain from
0 to 24 dB with 3 dB steps) which can be controlled via the
L3-bus/I
2
C-bus interface.
8.2.1 A
PPLICATION WITH 2V(RMS) INPUT
In applications in which a 2 V (RMS) input signal is used,
a 15 kΩ resistor must be used in series with the input of the
ADC (see Fig.3). This forms a voltage divider together with
the internal ADC resistor and ensures that only 1 V (RMS)
maximum is input to the IC. Using this application for a
2 V (RMS) input signal, the gain switch must be set to
0 dB. When a 1 V (RMS) input signal is input to the ADC in
the same application, the gain switch must be set to 6 dB.
An overview of the maximum input voltages allowed
against the presence of an external resistor and the setting
of the gain switch is given in Table 1.
Table 1 Application modes using input gain stage
handbook, halfpage
V
SSA(ADC)
VINL1
V
DDA(ADC)
VINR1
V
ADCN
VINL2
V
ADCP
VINR2
IPSEL
V
DDD
V
SSD
SYSCLK
L3MODE
L3CLOCK
V
ref
V
SSA(DAC)
VOUTL
V
DDA(DAC)
QMUTE
STATUS
VOUTR
STATIC
TEST1
DATAI
DATAO
WS
BCK
L3DATA
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
UDA1342TS
MGT017
Fig.2 Pin configuration.
RESISTOR
(15 kΩ)
PGA GAIN
MAXIMUM INPUT
VOLTAGE
Present 0 dB 2 V (RMS)
Present 6 dB 1 V (RMS)
Absent 0 dB 1 V (RMS)
Absent 6 dB 0.5 V (RMS)
handbook, halfpage
MGT018
V
ref
VINL1,
VINR1,
VINL2,
VINR2
2,
4,
6,
8
gain = 0 dB
10 kΩ
10 kΩ
15 kΩ
input signal
2 V (RMS)
UDA1342TS
Fig.3 Schematic of ADC front-end.
2000 Jul 31 9
NXP Semiconductors Product specification
Audio CODEC UDA1342TS
8.2.2 DOUBLE DIFFERENTIAL MODE
Since the UDA1342TS is equipped with two stereo ADCs,
these two pairs of stereo ADCs can be used to convert a
single stereo signal to a signal with a higher performance
by using the ADCs in the double differential mode.
This mode and the input signals, being channel 1 or 2 as
input to the double differential configuration, can be
selected via the L3-bus/I
2
C-bus interface.
8.3 Decimation filter (ADC)
The decimation from 64f
s
to 1f
s
is performed in two stages.
The first stage realizes a characteristic with a
decimation factor of 8. The second stage consists of three
half-band filters, each decimating by a factor of 2. The filter
characteristics are shown in Table 2.
Table 2 Decimation filter characteristics
8.4 Digital mixer (ADC)
The two stereo ADC outputs are mixed with gain
coefficients from +24 to 63.5 dB to be set via the
microcontroller interface.
In front of the mixer there is a DC filter. In order to prevent
clipping, it is needed to filter out the DC component before
mixing or amplifying the signals.
The mixing function can be enabled via the microcontroller
interface.
8.5 Interpolation filter (DAC)
The digital interpolation filter interpolates from 1f
s
to 64f
s
by means of a cascade of FIR filters. The filter
characteristics are shown in Table 3.
Table 3 Interpolation filter characteristics
8.6 Mute
Muting the DAC will result in a cosine roll-off soft mute,
using 32 × 32 = 1024 samples in the normal mode: this
results in 24 ms at f
s
= 44.1 kHz. The cosine roll-off curve
is illustrated in Fig.4.
This cosine roll-off functions are implemented in the DAC
data path before the digital mixer and before the master
mute (see Fig.5).
In the L3-bus and I
2
C-bus mode, the setting of the master
mute can be overruled always by pin QMUTE. This quick
mute uses the same cosine roll-off, but now for only
32 samples: this is 750 μs at f
s
=44.1kHz.
8.7 Digital mixer (DAC)
The ADC output signal and the digital interface input signal
can be mixed without an external DSP (see Fig.5).
This mixer can be controlled via the microcontroller
interface.
In order to prevent clipping when mixing two 0 dB signals,
the signals are attenuated digitally by 6dB before mixing.
After mixing the signal is gained by 6 dB after the master
volume. This way clipping at the digital mixer is prevented.
After the 6 dB gain, the signals can clip again, but this
clipping can be removed by decreasing the master
volume.
ITEM CONDITION VALUE (dB)
Pass-band ripple 0 to 0.45f
s
±0.01
Pass-band droop 0.45f
s
0.2
Stop band >0.55f
s
70
Dynamic range 0 to 0.45f
s
>135
ITEM CONDITION VALUE (dB)
Pass-band ripple 0 to 0.45f
s
±0.025
Stop band >0.55f
s
60
Dynamic range 0 to 0.45f
s
>135
xsin
x
-----------
⎝⎠
⎛⎞
4
handbook, halfpage
01051525
1
0
0.8
MGU119
20
0.6
0.4
0.2
t (ms)
mute
factor
Fig.4 Mute as a function of raised cosine roll-off.

UDA1342TS/N1,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC AUDIO CODEC 24BIT 28SSOP
Lifecycle:
New from this manufacturer.
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