2000 Jul 31 16
NXP Semiconductors Product specification
Audio CODEC UDA1342TS
8.15.4 DATA WRITE MODE
The data write format is given in Table 13 and illustrated
in Fig.9.
When writing data to a device four bytes must be sent:
1. One byte with the device address, being ‘01X0 1000’
where ‘X’ stands for the IPSEL value, including ‘01’ for
signalling write to the device.
2. One byte starting with a logic 0 for signalling write
followed by 7 bits indicating the register address.
3. One byte which is the Most Significant Data (MSD)
byte 1.
4. One byte which is the Least Significant Data (LSD)
byte 2.
8.15.5 D
ATA READ MODE
The data write format is given in Table 14 and illustrated
in Fig.10.
When reading from the device, a prepare read must first be
done. After the prepare read, the device address is sent
again. The device then returns with the register address,
indicating whether the address was valid or not, and the
data of the register.
The data read mode is explained below:
1. One byte with the device address, being ‘01X0 1000’
where ‘X’ stands for the IPSEL value, including ‘01’ for
signalling write to the device.
2. One byte is sent with the register address which needs
to be read. This byte starts with a logic 1, which
indicates that there will be a read action from the
register.
3. One byte with the device address including ‘11’ is sent
to the device. The ‘11’ indicates that the device must
write data to the microcontroller.
4. The device now writes the requested register address
on the L3-bus, indicating whether the requested
register was valid (logic 0) or invalid (logic 1).
5. The device writes data from the requested register to
the L3-bus with the MSD byte 1 first, followed by the
LSD byte 2.
Table 13 L3-bus format for data write
Table 14 L3-bus format for prepare read and read data
L3MODE DATA TYPE
FIRST IN TIME LAST IN TIME
BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
Address device address 01IPSEL01000
Data transfer 1 register address 0 A6 A5 A4 A3 A2 A1 A0
Data transfer 2 MSD byte 1 D15 D14 D13 D12 D11 D10 D9 D8
Data transfer3LSD byte2 D7D6D5D4D3D2D1D0
L3MODE DATA TYPE
FIRST IN TIME LAST IN TIME
BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
Prepare read
Address device address 01IPSEL01000
Data transfer 1 register address 1 A6 A5 A4 A3 A2 A1 A0
Read data
Address device address 11IPSEL01000
Data transfer 1 register address 0/1 A6 A5 A4 A3 A2 A1 A0
Data transfer 2 MSD byte 1 D15 D14 D13 D12 D11 D10 D9 D8
Data transfer3LSD byte2 D7D6D5D4D3D2D1D0
2000 Jul 31 17
NXP Semiconductors Product specification
Audio CODEC UDA1342TS
MGS75
3
L
3CLOCK
L3MODE
L3DATA
0
write
L3 wake-up pulse after power-up
device address
DOM bits
register address
data byte 1 data byte 2
10
Fig.9 Data write mode for L3-bus version 2.
MGS75
4
L
3CLOCK
L
3MODE
L
3DATA
0
read
valid/non-valid
device address
prepare read send by the device
DOM bits
register address device address register address
data byte 1 data byte 2
111
0/1
1
Fig.10 Data read mode for L3-bus version 2.
2000 Jul 31 18
NXP Semiconductors Product specification
Audio CODEC UDA1342TS
8.16 I
2
C-bus interface
Besides the L3-bus mode the UDA1342TS supports the
I
2
C-bus mode; all the features can be controlled by the
microcontroller with the same register addresses as used
in the L3-bus mode.
The exchange of data and control information between the
microcontroller and the UDA1342TS in the I
2
C-bus mode
is accomplished through a serial hardware interface
comprising the following pins and signals:
L3CLOCK: Serial Clock Line (SCL)
L3DATA: Serial Data line (SDA).
The clock and data timing of the I
2
C-bus transfer is shown
in Fig.15.
8.16.1 A
DDRESSING
Before any data is transmitted on the I
2
C-bus, the device
which should respond is addressed first. The addressing is
always done with the first byte transmitted after the START
procedure (S).
8.16.2 S
LAVE ADDRESS
The UDA1342TS acts as a slave receiver or a slave
transmitter. Therefore, the clock signal SCL is only an
input signal. The data signal SDA is an input or output
signal (bidirectional line).
The UDA1342TS slave address format is shown in
Table 15.
Table 15 I
2
C-bus slave address format
The slave address bit IPSEL corresponds to the hardware
address pin IPSEL which allows selecting the slave
address.
8.16.3 R
EGISTER ADDRESS
The UDA1342TS register address format is given in
Table 16.
Table 16 I
2
C-bus register address format
The register mapping of the I
2
C-bus and L3-bus interfaces
is the same (see Section 9).
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
001101IPSEL R/W
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
0 A6A5A4A3A2A1A0

UDA1342TS/N1,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC AUDIO CODEC 24BIT 28SSOP
Lifecycle:
New from this manufacturer.
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