2000 Jul 31 35
NXP Semiconductors Product specification
Audio CODEC UDA1342TS
t
su(L3)D
L3MODE set-up time in data
transfer mode
190 −− ns
t
h(L3)D
L3MODE hold time in data
transfer mode
190 −− ns
t
stp(L3)
L3MODE stop time in data
transfer mode
190 −− ns
t
su(L3)DA
L3DATA set-up time in address
and data transfer mode
190 −− ns
t
h(L3)DA
L3DATA hold time in address and
data transfer mode
30 −− ns
t
su(L3)R
L3DATA set-up time for read data 50 −− ns
t
h(L3)R
L3DATA hold time for read data 360 −− ns
t
en(L3)R
L3DATA enable time for read data 380 −− ns
t
dis(L3)R
L3DATA disable time for read
data
50 −− ns
I
2
C-bus interface timing (see Fig.15)
f
SCL
SCL clock frequency 0 − 400 kHz
t
LOW
SCL LOW time 1.3 −− μs
t
HIGH
SCL HIGH time 0.6 −− μs
t
r
rise time SDA and SCL note 4 20 + 0.1C
b
− 300 ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Notes
1. The typical value of the timing is specified at 48 kHz sampling frequency.
2. In order to prevent digital noise interfering with the L3-bus communication, it is best to have the rise and fall times as
small as possible.
3. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to
1
⁄
64fs
cycle.
4. C
b
is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
5. After this period, the first clock pulse is generated.
6. To be suppressed by the input filter.
t
f
fall time SDA and SCL note 4 20 + 0.1C
b
− 300 ns
t
HD;STA
hold time START condition note 5 0.6 −− μs
t
SU;STA
set-up time repeated START 0.6 −− μs
t
SU;STO
set-up time STOP condition 0.6 −− μs
t
BUF
bus free time between a STOP
and START condition
1.3 −− μs
t
SU;DAT
data set-up time 100 −− ns
t
HD;DAT
data hold time 0 −− μs
t
SP
pulse width of spikes note 6 0 − 50 ns
C
b
capacitive load for each bus line −−400 pF
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
