2000 Jul 31 20
NXP Semiconductors Product specification
Audio CODEC UDA1342TS
8.16.5 READ CYCLE
The read cycle is used to read data from the internal registers of the UDA1342TS to the microcontroller. The I
2
C-bus format for a read cycle is shown
in Table 18.
The format of the read cycle is as follows:
1. The microcontroller starts with a START condition S.
2. The first byte (8 bits) contains the device address 0011 01X and a write command (bit R/W
=0).
3. This is followed by an acknowledge (A) from the UDA1342TS.
4. The microcontroller then writes the register address where reading of the register content of the UDA1342TS must start.
5. The UDA1342TS acknowledges this register address.
6. Then the microcontroller generates a repeated START (Sr).
7. Again the device address 0011 01X is given, but this time followed by a read command (bit R/W
=1).
8. The UDA1342TS sends the two-byte data with the Most Significant Data (MSD) byte first and then the Least Significant Data (LSD) byte, where
each byte is acknowledged by the microcontroller (master).
9. The microcontroller stops this cycle by generating a negative acknowledge (NA).
10. The UDA1342TS then frees the I
2
C-bus and the microcontroller can generate a STOP condition (P).
Table 18 Master transmitter reads from UDA1342TS registers
Note
1. Auto increment of the register address is carried out if repeated groups of 2 bytes are transmitted.
ACKNOWLEDGE FROM UDA1342TS ACKNOWLEDGE FROM MASTER
DEVICE
ADDRESS
R/W
REGISTER
ADDRESS
DEVICE
ADDRESS
R/W
DATA
(1)
S 0011 01X 0 A 0XXX XXXX A Sr 0011 01X 1 A MSD1 A LSD1 A MSD2 A LSD2 A MSDn A LSDn NA P
8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits 8bits
